Bus Length Tuning Methodology; System Bus Tuning; Compensating For Package Trace Length Differences; Example Of Plc Compensation On The Motherboard - Intel EP80579 Manual

Equation 3. Total Flight Time
_
flight
5.6.3

Bus Length Tuning Methodology

Many buses, such as memory and bus, require length tuning a group of signals. A
common way to do this is by routing the bus first to determine what the approximate
length range is, then picking an arbitrary signal. Sometimes this signal may be the
most difficult one to route or adjust to tune. Using the PCB trace length for this signal,
the solution space of remainder signals and strobes in the group can be determined.
Intel is able to provide a length tuning calculator spreadsheet. The calculator uses all
the specific routing parameters specified in previous section (minimum and maximum
lengths, tolerances, signal groups, and so on) to determine the solution space for the
bus in question.
5.7

System Bus Tuning

Routing PCB system buses (for example, DDR2 memory bus) requires length matching
within source synchronous groups. As a result, propagation-based length matching is
used to account for the strobe-to-signal skew effects. Propagation-based length
matching is described in the next section, followed by a routing example.
5.7.1

Compensating for Package Trace Length Differences

The first factor in length matching involves compensating for package trace length
differences for signals within the same strobe group. The package trace length is
defined as the trace segment between the die pad and component package pin. The
package lengths on the processor and the EP80579 introduce skew between different
signals as illustrated in the example given in
Note: Component A in
uses a strobe and data signal, which happen to have the shortest and longest package
trace lengths respectively.
Figure 31. Package Trace Length Differences
Data Signal
Die Pad
Strobe Signal
Die Pad
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
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Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns
_
component1 length
time
=
component1_
velocity
Figure 31 represents a memory or I/O controller hub. This example
Component A
Longest Package Trace Length
Shortest Package Trace Length
_ component
PCB length
+ +
_
PCB velocity component
Figure 31.
Delta
PLC
Delta
Order Number: 320068-005US
_
2
length
_
2
velocity
Component Pin
May 2010