Development Board System Management - Smbus Block Diagram - Intel EP80579 Manual

System Management Bus (SMBus) Interface—Intel
Line
Figure 121. Development Board System Management - SMBus Block Diagram
V S B Y 3_3
0-oh m em pty
S M Bu s he ader S IO 1*
T P M is not conne cted
to S M Bu s
EP80579's SMBus has many features for system management. The following sections
show an example implementation of system management portions of EP80579 in the
Development Board. The system platform may use a BMC on a separate system
management card, although this is not part of the Development Board implementation.
This card is used for enabling and validating multiple system management vendors.
Intel highly recommends an embedded solution with the BMC of choice. Any controller
can serve this function. This section provides an example of what was implemented in
the Development Board. The example below is one of the possible system management
solutions for the EP80579.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product
G P O 19
D efau lt D isa ble
V S B Y_S M B*
S D A
S C LK
V C C 3
S IO A ddr 0xD 8
S D A1 S D A 2
S C LK1 S C L K2
V S B Y 3_3
0-ohm
0 -ohm
0-ohm em pty
S M B us header S IO 2*
P C I E xp x8 C onn
(S lot #1)
Bo ard ID
P C I E xp x4 C onn
(S lot #2)
P C I E xp x4 C onn
(S lot #3)
P C I E xp x4 C onn
(S lot #4)
P C I E xp x4 C onn
(S lo t #5)
SM Bus Block Diagram
LA N contro ller
E P 80579
IIC H
E P80 579
S M Link*
S M L ink
0-o hm V S B Y_S M B*
A dd r 0x44
G P O 20
D efault E nable
V C C 3
P C A 9515 P C A9 515
E N E N
S M B u s A R ep eater S M B us B R epe ater
SM B us hea der A*
E P 80579 IM C H
A dd r 0x 60
C K 41 0
A dd r 0X D 2
D B 80 0
A ddr 0x D C
IT P
M a ster
N ote:
S M B us h eader is a 1x3 for heade r 1:D A TA 2:G N D 3:C LK
S M Bu s he ader
* in N etnam es repre sen ts C L K and D A T
1 D ata
S M Link[0] = C LK a nd S M Link[1] = D A T
2 G round S M B S C L and S M B S D A from IM C H
3 C lock
V S B Y 3_3
S M B us heade r*
G P O 21
D efault D isab le
V C C 3
P C A 9515
E N
S M B us C R ep eater
S M B us head er B* S M B u s hea der C *
M ezzaine 0
D IM M _0
A ddr D e term in ed by C ard
A ddr 0xA 4
M ezzaine 1
D IM M _1
A ddr D e term in ed by C ard
A ddr 0xA 6
M ezzaine 2
A ddr D e term in ed by C ard
M ezzaine 3
A ddr D e term in ed by C ard
LE B C onne ctor
A ddr D e term in ed by C ard
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