Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Specification
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Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Specification

Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Specification

Xeon processor 5300 series specification update
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Intel® Xeon® Processor 5300 Series

Specification Update

December 2010
Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on
request.
Order Number: 315338-020

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Summary of Contents for Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor

  • Page 1: Specification Update

    Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
  • Page 2 WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

  • Page 3: Table Of Contents

    Contents Revision History ......................4 Preface ........................5 Summary Tables of Changes..................7 Identification Information ..................17 Errata ........................19 Specification Changes....................53 Specification Clarifications ..................54 Documentation Changes ..................55 Intel® Xeon® Processor 5300 Series Specification Update, December 2010...

  • Page 4: Revision History

    Update errata AJ56 and AJ61 March 2009 Added errata AJ124 and AJ125 -018 July 2009 Added Specification Change AJ1 -019 Added errata AJ126 March 2010 -020 Added errata AJ127, deleted AJ1 December 2010 Intel® Xeon® Processor 5300 Series Specification Update, December 2010...

  • Page 5: Preface

    Affected Documents Document Number/ Document Title Location Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 315569 Note: Contact your Intel representative for the latest revision and document number of this document. Related Documents Document Number/ Document Title Location ® AP-485, Intel...
  • Page 6 Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). Intel® Xeon® Processor 5300 Series Specification Update, December 2010...

  • Page 7: Summary Tables Of Changes

    The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® Xeon® Processor 5300 Series product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
  • Page 8 Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel®...
  • Page 9 AX = Intel® Xeon® processor 5400 series AY = Intel® Xeon® processor 5200 series AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Pro- cess AAA= Intel® Xeon® processor 3300 series AAB= Intel® Xeon® E3110 Processor AAC= Intel®...
  • Page 10 Global Pages in the Data Translation Look-Aside Buffer (DTLB) May AJ21 Plan Fix Not Be Flushed by RSM instruction before Restoring the Architectural State from SMRAM Sequential Code Fetch to Non-canonical Address May have Non- AJ22 Plan Fix deterministic Results Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 11 Performance Monitor IDLE_DURING_DIV (18h) Count May Not be AJ44 Plan Fix Accurate AJ45 No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM AJ46 No Fix ShutdownCondition May Disable Non-Bootstrap Processors Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 12 In Single-Stepping on Branches Mode, the BS Bit in the Pending- AJ72 Plan Fix Debug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM-Exit on a MOV to CR8 Instruction Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 13 Plan Fix SYSEXIT and SYSRET Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is AJ95 No Fix Counted Incorrectly for PMULUDQ Instruction Storage of PEBS Record Delayed Following Execution of MOV SS or AJ96 No Fix Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 14 WRMSR to an MTRR Mask PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR AJ106 No Fix Information Overlap of an Intel® VT APIC Access Page in a Guest with the DS AJ107 Plan Fix Save Area May Lead to Unpredictable Behavior AJ108...

  • Page 15: Specification Clarifications

    SPECIFICATION CHANGES Implementation of System Management Range Registers Specification Clarifications SPECIFICATION CLARIFICATIONS Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes DOCUMENTATION CHANGES None for this revision of this specification update. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...

  • Page 16: Identification Information

    Identification Information Component Identification via Programming Interface The Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following register contents: Family Model 0110 1111 Note: The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
  • Page 17 1,2 5,7,8,9 Notes: Intel® Xeon® Processor 5300 Series supports a Land Grid Array package with 771 lands in a 37.55 x 37.55 mm FC-LGA6 package Refer to the Intel® Xeon® Processor 5300 Series Datasheet for the VID values for these processors.

  • Page 18: Errata

    Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly de-assert. Implication: When this erratum occurs, the system may hang during shutdown. Intel has not observed this erratum with any commercially available systems or software. Workaround: None identified.
  • Page 19 RFLAGS.RF bit will be unconditionally cleared after execution of the SYSRET instruction. Implication: The SYSRET instruction can not be used if the RF flag needs to be set after returning from a system call. Intel has not observed this erratum with any commercially available software. Workaround: Use the IRET instruction to return from a system call, if RF flag has to be set after the return.
  • Page 20 #GP fault may not match the non-canonical address that caused the fault. Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None Identified.
  • Page 21 The value is lower by exactly one multiple of the maximum possible ratio. Workaround: Multiply the performance monitor value by the maximum possible ratio. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 22 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system. Workaround: Avoid code that wraps around segment limit.
  • Page 23 Due to this erratum, the processor may transfer control to an unintended address. The result of fetching code at that address is unpredictable and may include an unexpected trap or fault, or execution of the instructions found there. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 24 Reserved Bit settings in VM-exit Control Field Problem: Processors supporting Intel® Virtualization Technology (Intel® VT) can execute VMCALL from within the Virtual Machine Monitor (VMM) to activate dual-monitor treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to values inconsistent with VMX Capability MSRs, VMCALL may not VMFail.
  • Page 25 Execute Disable Bit functionality. Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 26 4G bytes for 32 bit address size. Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or STOS operations to re-execute. Intel has not observed this erratum with any commercially available software. Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than the address space size (64K for 16-bit address size and 4G for 32-bit address size).
  • Page 27 Implication: In this case, the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, including a General Protection Fault (GPF) or other unexpected behaviors. In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system.
  • Page 28 Due to this erratum, the processor may livelock. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 29 The corresponding data if sent out as a BTM on the system bus will also be incorrect. Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 30 VM86 mode. Normally, operating systems should prevent interrupt task switches from faulting, thus the scenario should not occur under normal circumstances. Workaround: None Identified Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 31 Workaround: As recommended in the IA32 Intel® Architecture Software Developer’s Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum.
  • Page 32 Updating a page table entry by changing R/W, U/S or P bits without TLB shootdown (as defined by the 4 step procedure in "Propagation of Page Table and Page Directory Entry Changes to Multiple Processors" in volume 3A of the IA-32 Intel® Architecture Software Developer's Manual), in conjunction with a complex sequence of internal processor micro-architectural events, may lead to unexpected processor behavior.
  • Page 33 Under certain conditions as described in the Software Developers Manual section “Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this...
  • Page 34 Implication: None identified. Although the EFLAGS saved value may contain incorrect arithmetic flag values, Intel has not identified software that inspects the arithmetic portion of this value while handling page faults. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without a page fault.
  • Page 35 PEBS Buffer Overflow Status Will Not be Indicated Unless IA32_DEBUGCTL[12] is Set Problem: IA32_PERF_GLOBAL_STATUS MSR (38EH) bit [62] when set, indicates that a PEBS (Precise Event-Based Sampling) overflow has occurred and a PMI (Performance Monitor Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 36 VM-Exit on a MOV to CR8 Instruction Problem: In a system supporting Intel® Virtualization Technology, the BS bit (bit 14 of the Pending-Debug-Exceptions field) in the guest state area will be incorrectly set when all of the following conditions occur: •...

  • Page 37: Software Interrupts

    SSE instructions. Implication: The event monitor instruction SIMD_INST_RETIRED may report count higher than expected. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 38 1, a MOV instruction from CR8 with a 16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and leave bits 63:16 at the destination register unmodified, instead of storing zeros in them. Implication: Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 39 Software that uses non-temporal data without proper serialization before accessing the non-temporal data may observe data in wrong program order. Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section “Buffering of Write Combining Memory Locations” will operate correctly.
  • Page 40 (U/S) or Present (P) bits without immediate TLB shootdown (as described by the 4 step procedure in "Propagation of Page Table and Page Directory Entry Changes to Multiple Processors" In volume 3A of the Intel® 64 and IA-32 Architecture Software Developer's Manual), in conjunction with a complex sequence of internal processor micro- architectural events, may lead to unexpected processor behavior.
  • Page 41 LSD (Loop Stream Detector), as described in the Optimizing the Front End section of the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
  • Page 42 Even if the BR1# and Lock# terminations are always on or always off, VOL electrical specifications are not violated. Intel has not observed any functional failure due to this erratum.
  • Page 43 The performance monitoring event MISALIGN_MEM_REF may over count. The extent of over counting depends on the number of memory accesses retiring while the counter is active. Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...
  • Page 44 As an example, an access to a memory mapped I/O device may be incorrectly marked as cacheable, become cached, and never make it to the I/O device. Intel has not observed this erratum with any commercially available software.
  • Page 45 AJ107. Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Problem: Logging of a branch record or a PEBS (precise-event-based-sampling) record to the DS (debug store) save area that overlaps with the APIC access page may lead to unpredictable behavior.
  • Page 46 A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
  • Page 47 Guest Interruptibility-State Field ® Problem: As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel 64 and IA- 32 Architectures Software Developer’s Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the “use TPR shadow",...
  • Page 48 WC memory operations. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 49 Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 50 Implication: Software may erroneously infer that a page fault was due to a reserved-bit violation when it was actually due to an attempt to access a not-present page. Intel has not observed this erratum with any commercially available software. Workaround: Page-fault handlers should ignore the RSVD flag in the error code if the P flag is 0.
  • Page 51 Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. Intel® Xeon® Processor 5300 Series Specification Update, December 2010...

  • Page 52: Specification Changes

    SMM (System Management Mode) code and data reside in SMRAM. The SMRR interface is an enhancement in Intel® 64 and IA-32 Architectures to limit cacheable reference of addresses in SMRAM to code running in SMM. The SMRR interface can be configured only by code running in SMM.

  • Page 53: Specification Clarifications

    Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly.

  • Page 54: Documentation Changes

    All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation. Note: Documentation changes for Intel® 64 and IA-32 Architecture Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document Intel®...
  • Page 55 Intel® Xeon® Processor 5300 Series Specification Update, December 2010...

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