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Figure 124. Development Board LPC Interface Block Diagram
E P80579
The routine and topology guidelines in
• Ten layer stack up
• LPC routing used layer 8
• Trace impedance 50 Ω ±10%
• LPC clock traces should be trace length matched. Maximum trace length mismatch
between clocks coming from the clock driver should be no greater that 250 mils.
Figure 125. Topology of LPC Interface
D evice 1
Figure 126
routing for all signals except clock:
• Daisy chain all signals to every device on the bus
• Use a total of five or fewer devices on the LPC bus
• The EP80579 can be placed anywhere in the bus daisy chain (can be in the middle
or at the end of the chain)
• There is no length matching requirement among the signals, as long as each signal
meets the length target
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
188
®
Intel
EP80579 Integrated Processor Product Line—Low Pin Count (LPC) Interface
B uffer to
P ort 80
LP C Interface
D evice 2
T L1
T L2
and
Table 70
show the EP80579's LPC interface design recommendation
Trusted-
Firm W are H ub
P latform
(FW H )
M odule
(TP M )
Figure 125
are based on the following:
D evice 3
D evice 4
T L3
S uper
IO
D evice 5
T L4
May 2010
Order Number: 320068-005US
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