Table of Contents
Advertisement
10.0
PCI Express* Interface
The EP80579 provides one configurable x8 PCI Express interface (Port A or PEA0) with
a maximum theoretical bandwidth of 4 GByte/s. Port A may alternatively be configured
as a 2x4 or a 2x1 (PEA0 and PEA1). This interface is referred to throughout this
document as the PCI Express Port A (PEA). The EP80579 may be configured as x8; in
that case the reference is PEA. The EP80579 may also be configured in x4 mode; in
which case there are two available x4 ports referred to as PEA0 and PEA1.
PCI Express is a dual-simplex point-to-point serial differential low voltage interconnect.
A PCI Express topology can contain a host bridge and several endpoints. The raw bit
rate on the data pins is 2.5 Gbit/sec/lane/direction at introduction. Maximum
theoretical bandwidth realized on the x8 PCI Express interface of 2 GByte/s in each
direction simultaneously, for an aggregate of 4 GByte/s. Each port consists of a group
of transmitters and receivers located on the same chip. Each lane consists of a
transmitter and a receiver pair. A link between device ports is a collection of lanes (x1,
x4, and x8 width). All lanes within a port must transmit data using one frequency.
The point-to-point, serial PCI Express interconnect offers layout advantages over
traditional multi-drop parallel interconnects. The lower signal count of PCI Express
reduces the number of traces required to route the interconnect.
Each PCI Express packet is 8b/10b encoded with an embedded clock. The embedded
clock simplifies routing rules by removing the length matching requirements between
signal pairs, which virtually eliminates the serpentine and routing space required to do
so. Differential signaling produces lower EMI and crosstalk. The high bit rate for PCI
Express requires some design considerations for board designers. See
"PCI Express Layout Design Guidelines"
designers to perform simulation and validation testing that is necessary to ensure a
successful design.
The PCI Express lane topology consists of a transmitter (Tx) differential pair located on
one device connected to a receiver (Rx) differential pair on a second device. One of the
devices may be located on the baseboard or an add-in card in which one or more
connectors may be present.
Each lane is AC coupled between its corresponding transmitter and receiver. The AC
coupling capacitor is located on the board close to the transmitter side. Each end of the
link is terminated on-die into nominal 100Ω differential DC impedance. Board
termination is not required. The differential signals from the transmitter must be
connected to the differential signals at the receiver.
interconnect.
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
135
®
Intel
EP80579 Integrated Processor Product Line—PCI Express* Interface
for more details. Intel encourages platform
Section 10.1,
Figure 86
shows the PCI Express
Order Number: 320068-005US
May 2010
Advertisement
Table of Contents
