System Management Sio Implementation - Intel EP80579 Manual

System Management Bus (SMBus) Interface—Intel
Line
Figure 122. System Management SIO Implementation
FET
AMP
3.3V 3.3V
10
kO
Notes:
1. This is an example for the EP80579 SMBus interface implementation in the EP80579
Development Board. This diagram idoes not present every signal. See the EP80579 Development
Board schematics for more details.
2. The Optional BMC connection is not implemented in the EP80579 Development Board.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product
Aux Fan
Aux Fan
PWM PWM
FAN FAN
PWM PWM
3.3V 3.3V
FAN FAN
10 10 10
kO kO kO
10
kO
PWM PWM
FAN FAN
FET
AMP
EP80579 Fan
CTS
DCD
DSR
DTR
RTS
RXD
TXD
RI
SERIRQ
PCICLK
LAD[3:0]
EP80579
LFRAME#
LDRQ0#
GPIO
SUSCLK
0 O
0 O
SIO
FANOUT
(PWM1)
3.3V 3.3V
10
kO
FANIN_x
(FANTACHn)
GP
FANOUT
(PWM2)
CTS1_N
CTS1# CTSM#
DCD1_N
DCD1# DCDM#
DSR1_N
DSR1# DSRM#
DTR1_N
DTR1# DTRM#
RTS1_N
RTS1# RTSM#
RXD1
SINM
RXD1
TXD1
TXD1 SOUTM
RI1
RI1
SCLK
SDA
CK410
CLK_
33
3.3V
8.2 kO
OPTIONAL BMC Connection
(not implemented in EP80579
DP)
System Management
Connector
SMC_SECURE
_MODE_KB
EMP_CTS#
EMP_DCD#
EMP_DSR#
EMP_DTR#
EMP_RTS
EMP_SIN
EMP_SOUT
SMC_RI
EMP_RI
EMP_XCVR_
EMP_XCVR_DISA
DISABLE
BLE
3.3V
8.2
kO
LPC_SERIRQ
SMC_33MHZ_CLK
LPC_AD[3:0]
LPC_FRAME#
LPC_DRQ#
OEM_GPIO1
SUS_CLK
100 O
SMC_CARD_
PRESENCE1#
SMC_CARD_
PRESENCE2#
SMC_CLR_CMOS#
SMC_SPKR#
May 2010
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