Turbo Mode; Simultaneous Multi-Threading; Enhanced Intel Speedstep Technology - Intel E42249-003 Product Specification

Functional Architecture
the chipset. The BIOS cannot guarantee which processor will be the system BSP, only that a
system BSP is selected. In the remainder of this document, system BSP is referred to as BSP.
The BSP is responsible for executing the BIOS POST and preparing the server to boot the
operating system. At boot time, the server is in virtual wire mode and the BSP alone is
programmed to accept local interrupts (INTR driven by programmable interrupt controller (PIC)
and non-maskable interrupt (NMI)).
As a part of the boot process, the BSP wakes each AP. When awakened, an AP programs its
memory type range registers (MTRRs) to be identical to those of the BSP. All APs execute a
halt instruction with their local interrupts disabled. If the BSP determines that an AP exists that
is a lower-featured processor or that has a lower value returned by the CPUID function, the BSP
switches to the lowest-featured processor in the server. The system management mode (SMM)
handler expects all processors to respond to an SMI.
3.1.4

Turbo Mode

The Turbo Mode feature opportunistically and automatically allows the CPU to run faster than
the TDP frequency if the processor is operating below specifications. Processor must be below
the power, temperature, and current specification limits. Turbo Mode increases performance of
both multi-threaded and single-threaded workloads. Turbo Mode operates under operating
system control - only entered when the operating system requests higher performance, such as
a transition from a P1 state to a P0 state. Ability to enter Turbo Mode is independent of the
number of active cores. Achievable processor turbo frequency is limited by the most
constraining of processor temperature, power, core Icc, and core ratio limits. Maximum Turbo
Mode frequency is dependent on the number of active cores. Each processor has a fixed
number of ―turbo bins that may have up to 3 bins above marked ―max freq bin . When
fewer cores are active, more turbo bins are available. Example: 1 Core 3 Turbo bins, 2 Cores 2
Turbo bins, 4 Cores 1 Turbo bin. If the processor supports this feature (it is not available in all
SKUs), the BIOS setup provides an option to enable or disable this feature. The default is
disabled.
3.1.5

Simultaneous Multi-Threading

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The Intel Xeon processors 5500 series supports Simultaneous Multi-Threading (SMT). The
BIOS detects processors that support this feature and enables SMT during POST.
If the processor supports this feature, the BIOS setup provides an option to enable or disable
this feature. The default is enabled.
The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors.
The SMBIOS Type 4 structure shows only the physical processors installed. It does not
describe the virtual processors.
3.1.6 Enhanced Intel
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Enhanced Intel SpeedStep
potentially improves system acoustics by allowing the system to dynamically adjust processor
voltage and core frequency
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SpeedStep Technology
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Technology helps reduce average system power consumption and
Intel order number: E42249-003
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Intel Server Board S5500BC TPS
Revision 1.0