Introduction; Address And Data Bus (32 Pins); Bus Control (9 Pins) - Motorola DSP56156 Manual

2.1

INTRODUCTION

The DSP56156 pinout is shown in Figure 2-2. The input and output signals on the chip are
organized into the 13 functional groups shown in Table 2-1. Figure 2-1 illustrates the relative
timing for the bus signals. See the timing descriptions in the technical data sheet for exact
information.
Table 2-1 Functional Group Pin Allocations
2.2

ADDRESS AND DATA BUS (32 PINS)

A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change in t0 and
specify the address for external program and data memory accesses. If there
is no external bus activity, A0-A15 remain at their previous values. A0-A15 are
three-stated during hardware reset or when the DSP is not bus master.
D0-D15 (Data Bus) - three state, active high, bidirectional input/outputs. Read data
is sampled on the trailing edge of t2, while write data output is enabled by the
leading edge of t2 and three-stated at the leading edge of t0. If there is no ex-
ternal bus activity, D0-D15 are three-stated. D0-D15 are also three-stated dur-
ing hardware reset.
2.3

BUS CONTROL (9 PINS)

PS/DS (Program /Data Memory Select) - three state active low output. This output
is asserted only when external data memory is referenced. PS/DS timing is the
same for the A0-A15 address lines. PS/DS is high for program memory access
and is low for data memory access. If the external bus is not used during an in-
struction cycle (t0,t1,t2,t3), PS/DS goes high in t0. PS/DS is in the high imped-
ance state during hardware reset or when the DSP is not bus master.
MOTOROLA

INTRODUCTION

Functional Group
Address and Data Buses
Bus Control
Interrupt and Mode Control
Clock and PLL
Host Interface or PIO
Timer Interface or PIO
SSI Interfaces or PIO
On-chip CODEC
On-chip emulation (OnCE)
Power (Vdd)
Ground (Vss)
APower (AVdd)
AGround (AVss)
Total
DSP56156 PIN DESCRIPTIONS
Number of Pins
32
9
4
3
15
2
10
7
4
9
15
1
1
112
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