Command Vector Register (Cvr); Host Control Register (Hcr) Bit Definitions - Motorola DSP56303 User Manual

24-bit digital signal processor
Table of Contents

Advertisement

DSP Core Programming Model
6.6.1
Host Control Register (HCR)
This read/write register controls the HI08 interrupt operation. Initialization values for HCR
bits are presented in Section 6.6.9, DSP-Side Registers After Reset, on page 6-22.
15
14
13
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 6-6. Host Control Register (HCR) (X:$FFFFC2)
Table 6-8. Host Control Register (HCR) Bit Definitions
Bit Number
Bit Name
15–5
4–3
HF[3 –2]
2
HCIE
1
HTIE
6-14
12
11
10
9
Reset Value
0
Reserved. Write to 0 for future compatibility.
0
Host Flags 2, 3
General-purpose flags for DSP-to-host communication. The DSP core can
set or clear HF[3–2]. The values of HF[3–2] are reflected in the interface
status register (ISR); that is, if they are modified by the DSP software, the
host processor can read the modified values by reading the ISR. These
two general-purpose flags can be used individually or as encoded pairs in
a simple DSP-to-host communication protocol, implemented in both the
DSP and the host processor software. The bit value is indeterminate after
an individual reset.
0
Host Command Interrupt Enable
Generates a host command interrupt request if the host command
pending (HCP) status bit in the HSR is set. If HCIE is cleared, HCP
interrupts are disabled. The interrupt address is determined by the host

command vector register (CVR).

NOTE: If more than one interrupt request source is asserted and enabled
(for example, HRDF is set, HCP is set, HRIE is set, and HCIE is set), the
HI08 generates interrupt requests according to priorities shown here. The
bit value is indeterminate after an individual reset.
0
Host Transmit Interrupt Enable
Generates a host transmit data interrupt request if the host transmit data
empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is
transferred from the HTX to the RXH, RXM, or RXL registers. If HTIE is
cleared, HTDE interrupts are disabled. The bit value is indeterminate after
an individual reset.
DSP56303 User's Manual
8
7
6
5
HF3
Description
Priority
Highest
Lowest
4
3
2
1
HF2
HCIE HTIE HRIE
Interrupt Source
Host Command (HCP = 1)
Transmit Data (HTDE = 1)
Receive Data (HRDF = 1)
0

Advertisement

Table of Contents
loading

Table of Contents