Operation At Serial Input Completion - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 14 8-BIT SERIAL I/O
● Serial input operation using external shift clock
Serial input operation with the external shift clock requires the settings shown in Figure 14.7-2 .
Figure 14.7-2 Settings Required for Serial Input Operation using External Shift Clock
SMR
SDR
DDR3
SSEL
When serial input operation is allowed, the value of the SI pin is captured and held in the SDR in
synchronization with the rising edge of the external shift clock. When serial input is completed,
immediately read the SDR and allow serial input operation (SMR: SST = 1) to prepare for the input of the
next data. In this case, when the 8-bit serial I/O is idle (state in which it is waiting for the output of the next
data), keep the external shift clock at a "H" level.
Figure 14.7-3 shows 8-bit serial input operation.
For MSB first
SDR
Serial input data
Shift clock
SIOF bit
SST bit
■

Operation at Serial Input Completion

At the rising edge of the shift clock for the serial data of the 8th bit, the interrupt request flag bit (SMR:
SIOF) is set to "1" and the serial I/O start bit (SMR: SST) is set (cleared) to "0".
328
bit7 bit6 bit5
SIOF SIOE SCKE
0
Reception data storage
: Used bit
0 : Set "0"
: Unused bit
: Set "1"
1
Figure 14.7-3 8-bit Serial Input Operation
bit7 bit6 bit5 bit4
#7 #6 #5 #4
#7 #6
0 1 2
Transfer start
bit4 bit3 bit2
SOE CKS1 CKS0
1 1
0
bit3 bit2 bit1
#3 #2 #1
#5 #4 #3 #2
3 4 5
Automatic clear at transfer end
bit1 bit0
BDS SST
1
0
SSEL
1
bit0
SI pin
#0
#1 #0
Clear via program
6 7
Interrupt request