Sequence Control Instructions - Omron CS1D DUPLEX SYSTEM - 10-2009 Operation Manual

Instruction Execution Times and Number of Steps
Instruction Mnemonic
SINGLE BIT SETB
SET
!SETB
SINGLE BIT RSTB
RESET
!RSTB
SINGLE BIT OUTB
OUTPUT
!OUTB
Note
9-5-3

Sequence Control Instructions

Instruction Mnemonic
END END
NO OPERA- NOP
TION
INTERLOCK IL
INTERLOCK ILC
CLEAR
MULTI-INTER- MILH
LOCK DIFFER-
ENTIATION
HOLD
MULTI-INTER- MILR
LOCK DIFFER-
ENTIATION
RELEASE
MULTI-INTER- MILC
LOCK CLEAR
JUMP JMP
JUMP END JME
CONDI- CJP
TIONAL JUMP
CONDI- CJPN
TIONAL JUMP
NOT
MULTIPLE JMP0
JUMP
MULTIPLE JME0
JUMP END
Code Length
(steps)
532 2
532 3
534 2
534 3
534 2
534 3
1. When a double-length operand is used, add 1 to the value shown in the
length column in the following table.
2. Not supported by Duplex CPU Systems.
Code Length
(steps)
001 1
000 1
002 1
003 1
517 3
518 3
519 2
004 2
005 2
510 2
511 2
515 1
516 1
Execution time ( s)
CPU6@H CPU6@S
(Duplex (Single
CPU) CPU)
0.24 0.24
(See note +21.44
2.)
0.24 0.24
(See note +21.44
2.)
0.22 0.22
(See note +21.42
2.)
Execution time ( s)
CPU6@H CPU6@S
(Duplex (Single
CPU) CPU)
5.5 5.5
0.02 0.02
0.06 0.06
0.06 0.06
(See note 6.1
2.)
7.5
8.9
(See note 6.1
2.)
7.5
8.9
(See note 5.0
2.)
5.7
0.38 0.38
--- ---
0.38 0.38
0.38 0.38
0.06 0.06
0.06 0.06
Section 9-5
Conditions
CPU4@S
(Single
CPU)
0.34 ---
+21.54 ---
0.34 ---
+21.54 ---
0.32 ---
+21.52 ---
Conditions
CPU4@S
(Single
CPU)
6.0 ---
0.04 ---
0.06 ---
0.06 ---
6.5 During interlock
7.9 Not during interlock
and interlock not
set
9.7 Not during interlock
and interlock set
6.5 During interlock
7.9 Not during interlock
and interlock not
set
9.7 Not during interlock
and interlock set
5.6 Interlock not
cleared
6.2 Interlock cleared
0.48 ---
--- ---
0.48 When JMP condi-
tion is satisfied
0.48 When JMP condi-
tion is satisfied
0.06 ---
0.06 ---
361