Omron CS1D DUPLEX SYSTEM - 10-2009 Operation Manual page 350

Index Registers
Index Register
Initialization
1,2,3...
IOM Hold Bit Operation
Direct Addressing
314
2. Bit Operand:
MOVR(560) 000013
SET +5,IR2
When the operand is treated as a bit, the leftmost 7 digits of the Index Reg-
ister specify the word address and the rightmost digit specifies the bit num-
ber. In this example, MOVR(560) sets the PLC memory address of
CIO 000013 (0C000D hex) in IR2. The SET instruction adds +5 from bit 13
to this PLC memory address, so it turns ON bit CIO 000102.
The Index Registers will be cleared in the following cases:
1. The operating mode is changed from PROGRAM mode to RUN/MONITOR
mode or vice-versa and the IOM Hold Bit is OFF.
2. The PLC's power supply is cycled and the IOM Hold Bit is OFF or not pro-
tected in the PLC Setup.
If the IOM Hold Bit (A50012) is ON, the Index Registers won't be cleared
when a FALS error occurs, when the operating mode is changed from PRO-
GRAM mode to RUN/MONITOR mode or vice-versa, or when power supply
recovers after a power interruption.
If the IOM Hold Bit (A50012) is ON, and the PLC Setup's "IOM Hold Bit Status
at Startup" setting is set to protect the IOM Hold Bit, and if the Index Registers
are not set to be shared between tasks (default setting), Index Registers will
be held in the following way when power is interrupted. For tasks that were
completed before power was interrupted, the values for the cycle during which
power was interrupted will be held. For tasks that were not completed before
power was interrupted, the values for the cycle before the cycle during which
power was interrupted will be held. For example, in a program with three
tasks, tasks 0, 1, and 2, if power is interrupted in the nth cycle during execu-
tion of task 1, then the execution result for the nth cycle of task 0 and the exe-
cution results for the (n 1)th cycle of tasks 1 and 2 will be held.
If the IOM Hold Bit (A50012) is ON, the PLC Setup's "IOM Hold Bit Status at
Startup" setting is set to protect the IOM Hold Bit, and the Index Registers are
set to be shared between tasks, Index Registers will not be held when the
PLC's power supply is reset (ON
undefined values. Be sure to set the values before continuing.
When an Index Register is used as an operand without a "," prefix, the instruc-
tion will operate on the contents of the Index Register itself (a two-word or
"double" value). Index Registers can be directly addressed only in the instruc-
tions shown in the following table. Use these instructions to operate on the
Index Registers as pointers.
With Single CPU Systems, the values of Index Registers are not stable when
a interrupt task is started. When using Index Registers inside interrupt tasks,
always MOVR (for all values except timer/counter PV) and MOVRW (for timer/
counter PV) inside the interrupt tasks to set the values of the Index Registers.
IR2
OFF ON). The Index Registers may take
Section 8-17