Timer Area - Omron CS1D DUPLEX SYSTEM - 10-2009 Operation Manual

Cs1d duplex system

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Timer Area

Note A TR bit is not required when there are no execution conditions after the

branch point or there is an execution condition only in the last line of the

instruction block.

The 4,096 timer numbers (T0000 to T4095) are shared by the TIM, TIMX,

TIMH(015), TIMHX(551), TMHH(540), TMHHX(552), TTIM(087),

TTIMX(555), TIMW(813), TIMWX(816), TMHW(815), and TMHWX(817)

instructions. Timer Completion Flags and present values (PVs) for these

instructions are accessed with the timer numbers. (The TIML(542),

TIMLX(553), MTIM(543), and MTIMX(554) instructions do not use timer num-

When a timer number is used in an operand that requires bit data, the timer

number accesses the Completion Flag of the timer. When a timer number is

used in an operand that requires word data, the timer number accesses the

PV of the timer. Timer Completion Flags can be used as often as necessary

as normally open and normally closed conditions and the values of timer PVs

can be read as normal word data.

With CS1D CPU Units, the refresh method for timer PVs can be set from the

CX-Programmer to either BCD or binary.

1. It is not recommended to use the same timer number in two timer instruc-

tions because the timers will not operate correctly if they are timing simul-

(If two or more timer instructions use the same timer number, an error will

be generated during the program check, but the timers will operate as long

as the instructions are not executed in the same cycle.)

2. The accuracy of timers is different for Duplex CPU Systems than for Single

CPU Systems or CS1-H CPU Units.

Section 8-13

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