Analog Devices ADRV9001 User Manual page 73

Reference Manual
DATA INTERFACE
adi_adrv9001_SsiTxRefClockPin_e txRefClockPin;
bool lvdsIBitInversion;
bool lvdsQBitInversion;
bool lvdsStrobeBitInversion;
uint8_t lvdsUseLsbIn12bitMode;
bool lvdsRxClkInversionEn;
bool cmosDdrPosClkEn;
bool cmosClkInversionEn;
bool DdrEn;
bool rxMaskStrobeEn;
} adi_adrv9001_SsiConfig_t;
In the data structure, the previously mentioned SSI modes are defined for each Tx/Rx channel.
and some default values. Additionally, find the detailed data structure and enumerator description in the API Doxygen help file.
Table 27. SSI Configuration Parameters
Parameter
ssiType
ssiDataFormatSel
numLaneSel
strobeType
lsbFirst
qFirst
txRefClockPin
lvdsIBitInversion
lvdsQBitInversion
lvdsStrobeBitInversion
lvdsUseLsbIn12bitMode
lvdsRxClkInversionEn
cmosDdrPosClkEn
cmosClkInversionEn
DdrEn
rxMaskStrobeEn
Figure 47 shows the Rx CMOS SSI with the DDR clock in relation to the strobe/data. To ensure the BBIC gets the best setup/hold timing
margin for RX CMOS DDR SSI, with
nEn=false), follow the Rx CMOS SSI output clock/strobe/data phase timing diagram shown in
CMOS SSI DDR configuration.
Figure 59. RX CMOS DDR SSI Default (Recommend) Output (cmosDdrPosClkEn=False, cmosClkInversionEn=False)
analog.com
Type Description
enum Set SSI type
enum Set SSI data format
enum Set SSI number of lanes
enum Set SSI strobe type
uint8_t Set LSB first
uint8_t Set Q data first
enum Set TX SSI reference clock output (TX_DCLK_OUT) options
bool Set LVDS SSI I bit differential pads polarity inversion
bool Set LVDS SSI Q bit inversion
bool Set LVDS SSI strobe bit inversion
uint8_t Set LVDS 12-bit mode
bool Set LVDS RX SSI clock inversion enable
bool Set CMOS DDR positive clock enable
bool Set CMOS DDR clock inversion enable
bool Set DDR mode enable
bool Set Rx Strobe Mask. Mask the Rx SSI Strobe when interface rate is multiple
times of sample rate. See the
Data Clock Rates section.
Table 27 RX CMOS DDR relative default SSI configurations (cmosDdrPosClkEn=false, cmosClkInversio-
Table 27
Receive CSSI with Two, Four, and Eight Times
Figure
ADRV9001
lists the SSI configuration parameters
Note
Default '0', MSB first
Default '0', I data first
Default 'false'
Default 'false,'' Rx SSI ignores
this field, I/Q lanes share the
configuration of "lvdsIBitInversion"
Default 'false''
Default '0', LVDS SSI uses 16-bit
mode
Default 'false'
Default 'false'
Default 'false'
Default 'false'
59. ADI recommends this default RX
Rev. 0 | 73 of 351