Digital Front End Components - Analog Devices ADRV9001 User Manual

Reference Manual ADRV9001
RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN
The LPF is calibrated during device initialization to ensure a consistent frequency corner across all devices. The 3dB bandwidth is set within
the device data structure and is profile dependent. The user could optionally tune the 1 dB/3 dB corner frequency of the LPF based on the
application. The ADRV9001 also allows to configure LPF at three different power consumption levels to save system power.
Analog-to-Digital Converter (ADC)
As mentioned earlier, the ADRV9001 provides a pair of HP ADCs and LP ADCs to achieve a flexible tradeoff between power consumption and
linearity performance. The HP ADC is based on the continuous time delta sigma (CTDS) architecture and is 5 bits wide. The LP ADC is based
on the voltage-controlled oscillator (VCO) architecture and is 16 bits wide. Each type of ADC is capable of accepting the same input voltage, but
the output bus width is different due to the different modulator orders and presence of linearity correction in the LP ADC.
The HP and LP ADCs provide a similar level of noise and dynamic range (full scale to thermal noise) performance. Therefore, the noise figure
(NF) performance is similar at the input. Even with slight NF difference at the device input, the difference at antenna input is smaller as a result
of the LNA gain in the front end. The major difference between the HP and LP ADC is the linearity performance and power consumption. The
intermodulation distortion (IMD) performance of HP ADC is slightly better than LP ADC, at the expense of higher power consumption. Refer to
the data sheet for detailed information.
Given the high dynamic range of both the HP and LP ADC, very little channelization or blocker filtering occur in the analog signal chain as the
HP ADC can simultaneously absorb weak signals and large blockers. The blocker suppression and channelization are then achieved efficiently
in the digital signal path.
Therefore, the HP ADC provides the maximum interferer tolerance and performance. The LP ADC provides the best power consumption
performance under a slightly relaxed interferer condition. Based on the application, select between HP and LP ADC for linearity and
power consumption performance tradeoff. In addition, dynamically switch HP ADC and LP ADC on the fly through API commands
adi_adrv9001_Rx_AdcSwitchEnable_Set( ) and adi_adrv9001_Rx_AdcSwitch_Configure( ). The first API function enables the ADC
switching feature, and it is called at the STANDBY state before initial calibrations. When the dynamic ADC switch is enabled, both the
HP ADC and LP ADC initial calibrations are performed. The second API configures the ADC switching functionality for a specified receiver
channel to operate in different modes. It is called at the CALIBRATED state after performing initial calibrations.
When the receiver Monitor Mode is enabled, the device might switch between the HP ADC and LP ADC to reduce power consumption.
Additional algorithms are employed in the ADRV9001 to compensate for the gain and delay differences while operating with different type of
ADCs, so that any internal switch is transparent to users.

DIGITAL FRONT END COMPONENTS

Decimation (DEC)
In receiver data chain, a series of decimators (organized into two different decimation stages) convert the ADC sample rate to a desired sample
rate in both the NB and WB modes. Figure 140 shows how to achieve the standard sampling rates for different standards through a flexible
combination of decimators in the data chain. For simplicity, any other non-DEC blocks are skipped in the diagram.
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