Analog Devices ADRV9001 User Manual page 21

Reference Manual
ADRV9001 EXAMPLE USE CASES
Table 6. Constraints and Limitations in a DMR Type Portable Radio Application (Continued)
Functionality Constraints and Limitations
Calibrations
During the receiver initialization sequence, ensure there are no signals present at the receiver input (external LNA must be disabled), and
appropriate termination must be present at the LNA output to avoid reflections of the receiver calibration tones. During the transmitter initialization
sequence, ensure the power amplifier is powered down to avoid unwanted emission of the transmitter calibration tones at the antenna.
For the transmitter tracking calibrations to operate, the ADRV9001 must access the receiver datapath during transmitter time slots.
AGPIOs Analog GPIOs (operating at 1.8 V level) can be used as read or write digital levels in the end user system. AGPIOs can be used to control the
states of external components (for example, RF Switch) or read back digital logic levels from the external components.
DGPIOs
For DMR type applications, the ADRV9001 supports RF Monitor mode of operation. DGPIO pins are used to send wake-up signal to the baseband
processor, and allow the baseband processor to move the ADRV9001 into Monitor mode using hardware pins (instead of API command).
Digital GPIOs can also be used to perform real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs operating as inputs control
the receiver gain, transmitter attenuation, AGC operation, and other elements of the ADRV9001 transceiver. Depending on the ADRV9001
operation, up to 4 GPIOs may be used by the data port interface.
AuxADC AuxADC can be used to monitor analog voltage (for example, a temperature sensor). AuxADC input voltage must not exceed 0.95 V.
AuxDAC AuxDAC can be used to control the VCXO responsible for generating the ADRV9001 device clock, generate a preconfigured ramp up/down signal
that can be used to control power amplifier bias, or control any circuitry that requires analog control voltage up to 1.75 V.
DEV_CLK_OUT The ADRV9001 provides a divided down version of the DEV_CLK reference clock input signal on the DEV_CLK_OUT output. This output is
intended to provide reference clock signal to the digital components in the overall system. This output can be configured to be active after power
up and before the ADRV9001 configuration stage.
Multichip Sync If there is no need for multichip synchronization, initialize the ADRV9001 using API functions only.
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