Mcs Substates (Internal Mcs State Transition); Mcs Procedure And Status Check - Analog Devices ADRV9001 User Manual

Reference Manual
MULTICHIP SYNCHRONIZATION
To have the phase synchronized, select the MCS and phase sync mode. In this case, consider phase synchronization as additional timing. As
frequency hops the PLL phase changes, it takes the additional time to do phase synchronization, as mentioned. This happens at the hop stage,
not at the initial stage.

MCS SUBSTATES (INTERNAL MCS STATE TRANSITION)

MCS Ready Substate
Definition: ADRV9001 clock is switched from the CLK PLL to reference clock. MCS is initialized. Ready to receive MCS pulses.
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MCS cannot be enabled with power saving mode. So, if the MCS command is sent with power saving mode > 0, ADRV9001 returns error.
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All ADRV9001 chips can enter MCS Ready asynchronously. This means BBIC should wait for the ready status notified by all the ADRV9001
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chips before issuing MCS pulses.
MCS Transition Substate
Definition: ADRV9001 is in MCS pulse 1-6 transition but not finished.
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BBIC or clock chip sends MCS pulses to all the ADRV9001 chips synchronously. BBIC monitors the MCS status and restarts MCS pulses, if
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needed, to all the ADRV9001 chips.
Internally, ADRV9001 keeps monitoring the MCS status. After detecting the fifth MCS pulse, switch the reference clock to the clock PLL.
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MCS Done Substate
Definition: MCS procedure is done. ADRV9001 is ready to move to the primed state.
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After receiving the sixth MCS, the substate is changed to MCS Done. ADRV9001 waits for the Primed command or MCS command again to
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rerun MCS.
If MCS is enabled, MCS substates are kept in the MCS Done status after the MCS procedure is finished regardless of the channel state,
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unless the chip is reinitialized.

MCS PROCEDURE AND STATUS CHECK

Before issuing MCS pulses, the ADRV9001 must be in the Calibrated state. Note this is the first Calibrated state after performing initial
calibrations. If there is a change to other states after the first calibrated state and then a change back to the calibrated state, MCS
does not work. Two APIs, adi_adrv9001_Mcs_Status_Get() and adi_adrv9001_Mcs_SwStatus_Get(), allow the BBIC to monitor the MCS
synchronization status during the entire MCS procedure. The first API verifies the synchronization status of the analog and digital subsystems
of the device after issuing one or all of the MCS pulses. The second API verifies the current state of adrv9001 software after issuing one or all
of the MCS pulses.
The MCS procedure and status check are described as follows:
1: Validate initial states before MCS
Validate the radio state is in the calibrated state and the device system state is not in the MCS but in normal mode
(ADI_ADRV9001_ARM_SYSTEM_NORMALMODE) by calling adi_adrv9001_Radio_State_Get() API.
2: Entering MCS Ready substate
Move all the ADRV9001 channels of interest to the MCS Ready substate by calling adi_adrv9001_Radio_ToMcsReady() API. This function
transitions all the ADRV9001 channels from the Calibrated state to MCS Ready substate. This is necessary before issuing all MCS pulses. Use
adi_adrv9001_Radio_State_Get() to get the system state, which should be at ADRV9001_ARM_SYSTEM_MCS and the MCS state, which
should be at ADRV9001_ARMMCSSTATES_READY. Use adi_adrv9001_Mcs_SwStatus_Get() API to make sure the MCS software state is
at ADRV9001_MCSSWSTATUS_READY.
3: Configure and send six MCS pulses
The BBIC or clock chip configures MCS with at least six pulses as inputs to the ADRV9001 MCS pin.
these pulses. This is a BBIC-specific function implemented by the user. adi_fpga9001_Mcs_Configure() and adi_fpga9001_Mcs_Start() are
examples in the SDK provided for the electric vehicle battery (EVB) system field programmable gate array (FPGA) board. Specify the pulse
width and wait time and make sure they satisfy the minimum requirement. While MCS is running, the ADRV9001 should be in the MCS
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ADRV9001
Table 41 specifies the timing for
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