Agc Clock And Gain Block Timing - Analog Devices ADRV9001 User Manual

Reference Manual
RECEIVER GAIN CONTROL

AGC CLOCK AND GAIN BLOCK TIMING

The AGC clock drives the AGC state machine. In the ADRV9001 device, the default AGC clock (to support a set of standard sample rates) is at
184.32 MHz. When an arbitrary sample rate is adopted in the receiver, the AGC clock varies.
The AGC state machine contains three states: the gain update counter, followed by slow loop settling (SLS) delay, and 5 AGC clock cycles
delay. The total time between the gain updates (gain update period) is a combination of slowLoopSettlingDelay and 5 AGC clock cycles. Note
that the first slowLoopSettlingDelay in darker gray is a part of the gain update counter.
Figure 160 outlines the operation of the AGC state machine. The diagram outlines possible gain change scenarios rather than a practical
example of AGC operation. The possible gain change scenarios are described as follows:
AGC gain attack within gain update counter, but more than an SLS delay before the gain update counter expiry: Because the SLS is typically
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several orders of magnitude smaller than the gain update counter, this is the most common gain decrement scenario. This type of AGC gain
attack is called gain attack type 1, as shown in
AGC gain attack within gain update counter, but within an SLS delay before the gain update counter expiry: This is a special case, which
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rarely occurs in applications. This type of AGC gain attack is called gain attack type 2, as shown in
AGC gain recovery at the end of the gain update counter: Note that when the fast recovery is enabled, the gain update counter is substituted
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with the low underrange interval. The gain attack can occur within the gain update counter when the fast attack is enabled. A gain recovery
event can only occur at the end of the gain update counter (or low underrange interval in the "fast recovery" mode), as previously discussed.
This is mainly to align the gain recovery (for the desired signal) with the frame or subframe boundary. After a gain attack, a gain change
counter with a value equal to the SLS delay is started. No further gain attacks are allowed while this counter is running. This allows to set the
minimum time between gain changes.
However, the gain change counter also prevents the AGC from moving from the gain update counter state to the slow loop settling delay state
as it must wait until the expiry of the SLS delay. Therefore, if a gain attack occurred very close to the end of the gain update counter state, the
gain change counter delays the start of the SLS state and shifts the gain recovery event, as shown in
gain recovery event is always aligned with the end of the gain update counter period.
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Figure 160. Delayed Gain Attack for Non-Delayed Gain Recovery
Figure 160.
ADRV9001
Figure 160.
Figure 161, whereas in Figure
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160, the