Hardware Operation - Analog Devices ADRV9001 User Manual

Reference Manual
ADRV9001 EVALUATION SYSTEM
2. IPv4 Subnet Mask to: 255.255.255.0
See Figure 284 for more details. Make sure the firewall on the PC does not block the following ports.
22 (SSH protocol)
►
55557 (access to the evaluation software on Xilinx platform).
►
Note that the ZYNQ ZCU102 evaluation platform IP address is set by default to: 192.168.1.10.
►

HARDWARE OPERATION

ZYNQ ZC706
1. Turn on the evaluation system by switching the ZYNQ ZC706 evaluation platform power switch (SW1) to 'on'. If the hardware is connected
correctly, two green LEDs (D801 and DS901) on the ADRV9001 evaluation card must be on.
2. The ZYNQ ZC706 evaluation platform uses a Linux operating system. It takes approximately 30 seconds before the system is ready for
operation and can accept commands from the PC software. Observe the boot status on the ZYNQ ZC706 evaluation platform GPIO LEDs
(L, C, R, O). The correct sequence has the following description:
a. After the SW1 is turned on, all four LEDs start flashing (moving single OFF light).
b. On the ADRV9001 evaluation board, the "System OK" LED also begins to flash.
c. These LEDs continue to flash in the same sequence through the FPGA boot up, TES connection, and TES program.
3. The reference clock signal (in the 10 MHz to 1000 MHz range, CW tone, +13 dBm max) is connected to the J501.
a. Note that the quality of the clock source used to generate the DEV_CLK directly impacts the overall system performance. Use a
high-quality, stable, and low-phase noise clock source.
4. To test the receiver on the ADRV9001 evaluation card, use a clean signal generator with low-phase noise to provide an input signal to the
selected receiver RF input. Use a shielded RG‑58, 50 Ω coaxial cable (1 m or shorter) to connect the signal generator.
5. To set the input level near the receiver's full scale, set the generator level (for a single tone signal) to approximately -15 dBm. This level
depends on the input frequency and gain settings through the path.
a. Note that no input signal is applied to the receiver input when performing an "init" calibration.
6. To test the transmitter, connect a spectrum analyzer to either transmitter output on the ADRV9001 evaluation card. Use a shielded RG‑58,
50 Ω coaxial cable (1 m or shorter) to connect the spectrum analyzer.
a. Terminate both transmitter outputs, either into spectrum analyzers or into 50 Ω, if unused. This is because the initial calibrations run on
both channels and can take a long time to complete if a transmitter channel is not correctly terminated.
7. Execute power-off using the TES or power down the ZYNQ ZC706 evaluation platform using the SW9 push button before powering off the
evaluation system by switching SW1 to "off".
ZYNQ ZCU102
1. Turn on the evaluation system by switching the ZCU102 evaluation platform power switch (SW1) to "on". If the hardware is connected
correctly, two green LEDs (D801 and DS901) on the ADRV9001 evaluation card must be on.
2. The ZCU102 evaluation platform uses a Linux operating system. It takes approximately 30 seconds before the system is ready for operation
and can accept commands from the PC software. Observe the boot status on the ZCU102 evaluation platform GPIO LEDs (DS37–DS40).
The correct sequence has the following description:
a. After the SW1 is turned on, all four LEDs start flashing (moving single OFF light).
b. On the ADRV9001 evaluation board the "System OK" LED also begins to flash.
c. These LEDs continue to flash in the same sequence through the FPGA boot up, TES connection, and TES program.
d. When boot is done, the "Init" LED is green and "Init Done" LED is "on" in the "Power" and "Status" LEDs.
3. The ADRV9001 reference clock signal (in the 10 MHz to 1000MHz range, CWtone, +13 dBm max) is connected to the J501.
a. Note that the quality of clock source used to generate the DEV_CLK directly impacts the overall system performance. Use a
high-quality, stable, and low-phase noise clock source.
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ADRV9001
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