Serial-Peripheral Interface (Spi); Spi Configuration; Spi Bus Signals - Analog Devices ADRV9001 User Manual

Reference Manual

SERIAL-PERIPHERAL INTERFACE (SPI)

The SPI bus provides the mechanism for digital control by a baseband processor. Each SPI register is 8 bits wide, and each register contains
control bits, status monitors, or other settings that control all device functions . This section is mainly an information-only section meant to
understand the hardware interface used by the baseband processor to control the device. All control functions are implemented using the API
detailed within this document. The following sections explain the specifics of this interface.

SPI CONFIGURATION

Configure the SPI settings for the device with different SPI controller configurations by configuring the member values of the
adi_adrv9001_SpiSettings_t data structure. The adi_adrv9001_SpiSettings_t data structure contains:
typedef struct adi_adrv9001SpiSettings{
uint8_t msbFirst;
uint8_t enSpiStreaming;
uint8_t autoIncAddrUp;
uint8_t fourWireMode;
adi_adrv9001_CmosPadDrvStr_e cmosPadDrvStrength;
} adi_adrv9001_SpiSettings_t;
Table 16 lists the parameters for this structure.
Table 16. SPI Settings Data Structure
Structure Member
MSBFirst
enSpiStreaming
autoIncAddrUp
fourWireMode
cmosPadDrvStrength
Note: Any value not listed in the table is invalid.
For more details, refer to the ADRV9001_API Doxygen file provided in the ADRV9001 SDK package.

SPI BUS SIGNALS

The SPI bus consists of the following signals:
Serial clock (SCLK)
►
Chip select bar (CSB)
►
Serial data input/output and serial data output (SDIO and SDO)
►
analog.com
Value Function
0x00 Least significant bit first.
0x01 Most significant bit first.
0x00 Disable SW feature. Section
describes this mode of operation.
0x01
Enable SW feature to improve SPI throughput. Section
fer
Not recommended as most registers in the ADRV9001 API are not consecu-
tive.
0x00
Autodecrement. Functionality to be used with SPI Streaming.
Sets address autodecrement -> next addr = addr -1
0x01
Autoincrement. Functionality to be used with SPI Streaming.
Sets address autoincrement -> next addr = addr +1
0x00
SPI hardware implementation ofusing 3-wire SPI (SDIO pin is bidirectional).
Note: ADI's FPGA platform always uses 4-wire mode.
0x01
SPI hardware implementation of using 4-wire SPI.
Note: Default mode for ADI's FPGA platform is 4-wire mode.
0x00 5 pF load at 75 MHz
0x01 100 pF load at 20 MHz
Multibyte Data Transfer
(SPI Streaming) describes this mode of operation.
ADRV9001
Default
0x01
(SPI Streaming) 0x00
Multibyte Data Trans-
0x01
0x01
0x01
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