Sample Delay And Read Delay - Analog Devices ADRV9001 User Manual

Reference Manual
MULTICHIP SYNCHRONIZATION
transition substate. Table 42 shows the detailed expected states after sending each pulse. Utilize this table to debug any problems that occur
during the MCS procedure.
Table 42. Expected States after Each MCS Pulse
adi_adrv9001_Radio_State_Get()
System State
After MCS PULSE 1 ARM_SYSTEM_MCS
After MCS PULSE 2 ARM_SYSTEM_MCS
After MCS PULSE 3 ARM_SYSTEM_MCS
After MCS PULSE 4 ARM_SYSTEM_MCS
After MCS PULSE 5 ARM_SYSTEM_MCS
After MCS PULSE 6 ARM_SYSTEM_MCS
Note that the first and second digital sync and the LVDS first and second sync complete to become true after the first pulse, which is ignored.
They are reset to false after the fourth pulse. The states after the fourth pulse reflect the correct expected states.
4: MCS done
After all six pulses are received, MCS is finished. At this point, ADRV9001 is in the MCS Done substate. Start to prime the channels to prepare
for normal operations.

SAMPLE DELAY AND READ DELAY

The ADRV9001 also supports the scenario where the data coming from/going to the SSI for multiple channels have different delays. This
is typically more important on the transmit side, where the data coming to the SSI has different delays. On the receive side, the baseband
processor manipulates the delay.
To mitigate this delay difference, the ADRV9001 provides the measurement from the last MCS pulse edge to the transmitter strobe for different
channels. This measurement is effective for all channels associated to the MCS, as the transmitter strobe of each channel can have a different
delay relative to the MCS pulse signal. The API function that achieves this is adi_adrv9001_Mcs_TxMcsToStrobeSampleLatency_Get(),
which takes the channel number and provides the latency, in samples, from the MCS to the transmitter strobe for the specified channel.
Once the latency is measured for all channels, refer to this as MCS_to_Strobe latency. Next, calculate the Sample Delay and Read Delay
separately, and set the delays into the ADRV9001 to achieve the same transmitter latency for all channels among all the ADRV9001 chips.
Sample Delay: It helps delay the ADRV9001 internal FIFO read point so that if MCS_to_Strobe is too big, then it delays the FIFO so that FIFO
saves less irrelevant information.
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adi_adrv9001_Mcs_SwStatus_
MCS State Get()
ARMMCSSTATES_READY MCSSWSTATUS_READY
ARMMCSSTATES_ MCSSWSTATUS_PULSE2_
TRANSITION RECEIVED
ARMMCSSTATES_ MCSSWSTATUS_PULSE3_
TRANSITION RECEIVED
ARMMCSSTATES_ MCSSWSTATUS_PULSE4_
TRANSITION RECEIVED
ARMMCSSTATES_ MCSSWSTATUS_DEVICE_
TRANSITION SWITCHED_TO_HSCLK
ARMMCSSTATES_ MCSSWSTATUS_DEVICE_
DONE SWITCHED_TO_HSCLK
ADRV9001
adi_adrv9001_Mcs_Status_Get(
)
N/A
CLK PLL (HP or LP) Reference
clock divider sync completed.
RF PLL (rf1 and/or rf2) reference
clock divider sync completed.
CLK PLL (HP or LP) SDM clock
divider sync completed.
RF PLL (rf1 and/or rf2) SDM
clock divider sync completed.
CLK PLL (HP or LP) digital clocks
sync completed and clock gen
divider sync completed.
RF PLL (rf1 and/or rf2)
Digital clocks sync completed and
clock gen divider sync completed.
CLK PLL (HP or LP) sync com-
pleted.
RF PLL (rf1 and/or rf2)
sync completed.
LVDS first sync completed (if in
LVDS mode).
First digital sync completed.
LVDS second sync completed (if
in LVDS mode).
Second digital sync completed.
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