Analog Gpio Operation - Analog Devices ADRV9001 User Manual

Reference Manual
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) AND INTERRUPT CONFIGURATION
TX2_DCLK_OUT± functionality when it is in the LVDS mode, or use either DGPIO_14 or DGPIO_15 as the Tx1 DCLK out if it is in the CMOS
mode.
Note: When the Tx DCLK OUT function is disabled, reuse the corresponding DGPIOs (DGPIO12/13 or DGPIO 14/15) only as input functions.

ANALOG GPIO OPERATION

The analog GPIO pins serve as the control pins for the external control elements, such as a digital step attenuator (DSA), low-noise amplifier
(LNA), external local oscillator (LO)/voltage-controlled oscillator (VCO) components, T/R switch of the TDD system, and so on. Alternatively,
analog GPIO pins provide the auxiliary DAC output.
Table 99 provides a high-level overview of the analog GPIO features.
Table 99. Summary of Analog GPIO Features
Feature Description
RX Gain Table External The RX gain table can include a column for 2-bit control of an external gain
Control Word element (LNA). Each Rx channel has 2 Analog GPIO pins associated with it.
RF Front-End Control Allows AGPIO timing to be associated with Tx/Rx_Enable to control the RF
front end.
Manual Pin Toggle Manually control the GPIO output level. API functions set output pin levels and
read the input pin levels.
Auxiliary DAC Output Allows the auxiliary DAC output on analog GPIO pins.
Receiver Gain Table External Control Word
The Receiver Gain Control section provides a complete description of the receiver gain table external control.
The ADRV9001 AGPIO output can control the external LNA gain. Each channel has two AGPIO control signals and achieves control of up to
four external LNA gain steps. adi_adrv9001_Rx_ExternalLna_Configure() enables and configures the external LNA gain control.
The AGPIOs for channel 1 and channel 2 must be in one analog GPIO (AGPIO) nibble, which means the four AGPIOs for external gain control
must be AGPIO[3:0] or AGPIO[7:4] or AGPIO[11:8]. For example, AGPIO_7/AGPIO_6 is for Rx1 external gain control, and AGPIO_5/AGPIO_4
for Rx2.
RF Front-End Control
To save the baseband processor control pins, the ADRV9001 provides the function to output the control signals through analog GPIO pins to
power up/down the external RF front-end components (i.e., LNA, transmitter gain blocks, Ext PLL) or switch the T/R switch of a TDD system.
For example, use a TX_ON, RX_ON output signal through the analog GPIOs and associated with the ADRV9001 transmitter/receiver enable
timing and state to enable/disable the power amplifier and LNA, respectively, or do the antenna switch.
To get the best timing control performance, there are dedicated AGPIOs for transmitter/receiver front-end control. AGPIO_0, AGPIO_1,
AGPIO_8, AGPIO_9 are associated with Tx1_Enable, Rx1_Enable, Tx2_Enable, Rx2_Enable, respectively.
The AGPIO for external RF front-end control is initialized in adi_adrv9001_gpio_ControlInit_Configure(), and the relative AGPIOs are
configured by the API adi_adrv9001_gpio_Configure().
Note: Once the AGPIO external RF front-end control is enabled, the receiver gain table external control can only use AGPIO[7:4].
Manual Pin Toggle
Like the manual pin toggle for digital GPIOs, this feature controls the logic level of individual analog GPIO pins. The adi_adrv9001_gpio_Man-
ualAnalogOutput_Configure() and adi_adrv9001_gpio_ManualAnalogInput_Configure() manually configure the analog GPIO output and
input, respectively. adi_adrv9001_gpio_OutputPinLevel_Set() and adi_adrv9001_gpio_InputPinLevel_Get() set and read the relative
analog.com
ADRV9001
GPIO Pins Available for Feature
Any analog GPIO, but Rx1/Rx2 external gain word must be in
one AGPIO nibble.
AGPIO_0 for Tx1
AGPIO_1 for Rx1
AGPIO_8 for Tx2
AGPIO_9 for Rx2
Any analog GPIO
AGPIO_0: AuxDAC0 output pin select
AGPIO_1: AuxDAC1 output pin select
AGPIO_2: AuxDAC2 output pin select
AGPIO_3: AuxDAC3 output pin select
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