Transmitter Signal Chain; Data Interface; Datapath - Analog Devices ADRV9001 User Manual

Reference Manual

TRANSMITTER SIGNAL CHAIN

The ADRV9001 device integrates dual direct-conversion (Zero-IF) transmitters. It supports both the time division duplex (TDD) and frequency
division duplex (FDD) modes, and is capable of transmitting both narrowband (NB) and wideband (WB) signals. It supports a wide range of
applications, such as DMR, P25, and TETRA, as examples of NB standards, and LTE as an example of WB standards.
In general, each transmitter consists of an independent I and Q signal path with separate digital filters, digital-to-analog converters (DAC),
analog transmit low-pass filters (LPF), and upconversion mixers. After mixers, an analog attenuator is employed to control the transmitter output
signal power.
Data from a baseband processor is input to the transmitter signal path through SSI. The serial data is converted to the parallel format through
the deframer and then the data is processed by interpolation filters. There are several signal conditioning functions, such as transmitter gain
control, power amplifier protection, digital predistortion (DPD), transmitter quadrature error correction (QEC), and transmitter LO leakage (LOL)
handling before the data is passed on to the DACs. The DAC outputs are filtered by LPF, upconverted to RF through the mixer, and attenuated
through the analog attenuator to prepare for RF transmission. The ADRV9001 device also supports frequency modulation (FM)/frequency shift
keying (FSK) for some NB applications.
Figure 126 shows the high level block diagram of the transmitter signal path.

DATA INTERFACE

The transmitter data interface supports several different interface rates and configurations. It has five differential pairs , i.e., 10 wires. The
interface is operated single-ended in the CMOS synchronous serial interface (CSSI) mode and differential in the LVDS synchronous serial
interface (LSSI) mode.
As mentioned earlier, the ADRV9001 supports many NB and WB standards. Depending on the selected standard and the specific symbol rate
chosen through the API profile, the interface clock rate can vary significantly. Note that CSSI is a slow-speed interface and cannot cover this
entire frequency range. For more details, see the

DATAPATH

Figure 127 shows the high level datapath composed of an analog front end (AFE) and a digital front end (DFE).
In the DFE subsystem, the SSI passes data to the transmitter preprocessing blocks, including a symbol mapping/interpolation and a 128-tap
programmable FIR filter (PFIR). The symbol mapping/interpolation is used for interpolation and/or symbol mapping necessary for certain NB
standards. Note that if it is configured as an interpolator, ensure proper filtering of the interpolation images in the PFIR. The PFIR is followed
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Figure 126. High Level Block Diagram of TX Signal Chain
Data Interface section.
Figure 127. Tx Datapath Block Diagram
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