Analog Devices ADRV9001 User Manual page 182

Reference Manual
RECEIVER GAIN CONTROL
Table 81. adi_adrv9001_GainControlCfg_t Structure Definition
Parameter
peakWaitTime
maxGainIndex
minGainIndex
gainUpdateCounter
attackDelay_us
slowLoopSettlingDelay
lowThreshPreventGainInc
changeGainIfThreshHigh
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Figure 163. Member Listing of adi_adrv9001_GainControlCfg_t Data Structure
Description
Number of gain control clock cycles to wait before enabling peak detectors
after a gain change.
Maximum gain index allowed. Must be greater than minGainIndex and be a
valid gain index.
Minimum gain index allowed. Must be less than maxGainIndex and be a
valid gain index.
Used as a decision period, with the detectors reset on this period. Gain
changes in the AGC mode can also be synchronized to this period
(the expiry of this counter). The full period is a combination of the
gainUpdateCounter and slowLoopSettlingDelay and a number of AGC
cycles.
The duration the AGC is held in reset when the Rx path is enabled.
Number of AGC clock cycles to wait after a gain change before the AGC
changes gain again.
Only relevant in peak and power detect AGC operation.1: If AGC is in
peak and power detect mode, then gain increments requested by the power
detector are prevented if there are sufficient peaks (APD/HB low threshold
exceeded count) above the apdLowThresh or hbUnderRangeHighThresh.0:
apdLowThresh and hbUnderRangeHighThresh do not care for gain
recovery.
Applicable in both the peak and peak and power detect modes.0: Gain
changes wait for the expiry of the gain update counter if a high threshold
ADRV9001
Min Value Max Value Default
Value
0 31 4
187 255 255
187 255 187
Depends on 4194303 11520
overload detector
AGC CLK
settings
cycles
0 63 10
0 127 16
0 1 0
0 3 3
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