Dev_Clk_In Phase Noise Requirements - Analog Devices ADRV9001 User Manual

Reference Manual
RF PORT INTERFACE INFORMATION
Implement the device clock input board traces connected to the device clock inputs balls with stripline transmission lines using inner copper
layers in the PCB stackup. The frequency of the device clock input signal can go as high as 1 GHz, and the stripline transmission line approach
provides better signal integrity of the clock signal, especially at higher frequency, as well as superior shielding of the RF emission of the device
clock signal.
The DEV_CLK_IN signal is available on the DEV_CLK_OUT pin.
after power up. Change this divider later on using an API command. Note that the DEV_CLK_OUT pin is a CMOS type pin with 80 MHz as its
maximum frequency of operation. It is intended to provide clock to the BBIC, on-board microcontroller, or audio CODEC type devices. It is not
intended for use by another RF sensitive IC.
For applications that use internal RF LOs, it is recommended to use 40 MHz or above as a DEV_CLK frequency to get the best in-band phase
noise.
There is a known issue with the DEV_CLK input working in the CMOS mode. When the applied DEV_CLK input signal is in range between 10
MHz to 30 MHz, internal RF LOs exhibit in-band phase noise degradation of around 10 dB.
If this phase noise degradation is not acceptable and it is mandatory to use the DEV_CLK below 30 MHz in the end application:
Connect the MODEA pin to GND, which enables the differential mode of operation for the DEV_CLK input circuitry.
►
Apply DEV_CLK as single-ended to DEV_CLK_IN + (E7 ball) and leave DEV_CLK_IN − (E8 ball) unconnected. Basically, use the same
►
hardware configuration as in the CMOS mode, outlined in
Ensure the amplitude of the applied signal does not exceed 1 V peak-to-peak. It is recommended to use a signal in the range of 400
►
mW peak-to-peak. The DEV_CLK_IN + (E7 ball) inputs, when operating in the LVDS mode, is biased on the device to around 200 mV
voltage level. A maximum of 400mV peak-to-peak amplitude ensures that the external clock stays compliant with the electrical specification
of DEV_CLK_IN + pin.

DEV_CLK_IN PHASE NOISE REQUIREMENTS

To prevent performance degradation, the DEV_CLK reference must be a very clean signal. The synthesizer provides best performance if the
applied reference is ideal. However, that is unrealistic.
degradation compared to an ideal DEVICE CLOCK. For different DEV_CLK frequencies, the table can be scaled appropriately. Clock source
with phase noise performance outlined in
provides reference information for the ADRV9001 operating with LTE type standards. Each standard determines its own DEV_CLK phase
noise requirements. As an example,
LMR type standards. Ideally, derive the DEV_CLK phase noise requirement from the user-specific application and its requirements set for the
adjacent channel rejection.
In general, using a higher phase noise source can degrade performance delivered by the ADRV9001 transceiver.
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Figure 249. Device Clock Input Series Equivalent Differential Impedance
Table 113
Figure
Table 114 lists the required phase noise of the DEV_CLK signal for a 1dB system PN
Table 115 (or better) allows the ADRV9001 to deliver data sheet performance. Note that
Table 115 provides recommendations for the DEV_CLK when the ADRV9001 is intended to operate with
describes the default division applied to the DEV_CLK_IN signal
247.
ADRV9001
Table 114
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