Analog Devices ADRV9001 User Manual page 144

Reference Manual ADRV9001
RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN
Figure 140. Decimation Schemes in Receiver Data Chain to Support Various Standards
Figure 140 shows that in the NB and WB mode, three different ADC output sample rates are first decimated to a common rate of 184.32 MHz in
standard use cases. Then, it is further converted to two different rates. One is 61.44 MHz for WB mode only and the other is 46.08 MHz for both
the NB and WB modes. All LTE standard modes are considered WB and the desired sample rate is further generated from both 61.44 MHz and
46.08 MHz through a decimation rate of 2 to 32. The DMR, FM, P25, and Tetra are NB modes, and the desired sample rate is further generated
from 46.08 MHz with a decimation rate of 160 to 1920.
For each decimator shown in Figure 140, there is a combination of lower rate decimators. For example, DEC/40 is implemented as a cascade
of DEC/10 and 2 DEC/2 decimators. In addition, the different decimation rates are achieved by strategically enabling and disabling some lower
rate decimators. For example, in WB mode, with an initial sample rate of 61.44 MHz, if all lower rate decimators are used, it can achieve a
decimation rate of 32. If two of the DEC/2 are disabled, a decimation rate of 8 can be achieved. All the decimation filters are carefully designed
to satisfy the system performance requirements.
With the arbitrary sample rate, the user could get an almost continuous range of sample rates from 24 kHz to 61.44 MHz, except for some
"dead zones" due to internal clocking constraints. Achieve this by adjusting the internal CLK PLL frequency as well as a flexible arrangement of
decimators.
DC Offset
The ADRV9001 receiver supports both IF and ZIF down conversions. The source of the DC offset is mainly from the receiver LO leakage
caused by the finite isolation between the LO and RF ports of a mixer, which is typical for silicon-based ICs. It generates a high DC component
at the center of the desired signal band, especially for ZIF operation. Through the datapath, the induced DC offset is amplified and reduces the
ADC dynamic range significantly. In addition to receiver LO leakage, the device mismatch in LPF and ADC also contributes to the DC offset
problem. Without properly correcting the DC offset, it can cause a negative impact on the system performance.
In the ADRV9001, a two-step approach estimates and corrects the DC offset. The first step comprises a DC estimation step in the digital
domain and a correction procedure in the analog domain, which is called RFDC. The second step is an all-digital DC offset estimation and
correction technique that estimates and corrects for any residual DC offset after the first step, which is called BBDC. BBDC is basically a notch
filter, and controls the width of the notch. The default value is 1/(2048*16), but can be changed for a wider or narrower notch.
The ADRV9001 also provides an option to enable an LO interference detection (LOID) algorithm. It optimizes the RFDC performance in the
presence of a blocker around DC. If a blocker is detected, then the LOID signals the RFDC to freeze the data correction updates, as performing
updates in the presence of a blocker degrades the performance of RFDC. If a blocker is not detected, then the LOID feature signals the RFDC
to resume its operation. The LO interference detection threshold is configurable. By default, it is set as -61 dBFS. When the LO interference is
above the threshold, RFDC is disabled, and when the interference is below the threshold, RFDC is re-enabled.
analog.com Rev. 0 | 144 of 351