Analog Devices ADRV9001 User Manual page 274

Reference Manual
PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Figure 257. ADRV9001 Power-Supply Domains with Connection Guidelines, Some Internal LDOs Bypassed, 1.0V Analog Domain Required
Place ceramic 4.7 µF bypass capacitors at the VRFVCO2_1P0, VRFVCO1_1P0, VRX2LO_1P0, VRX1LO_1P0, VCLKVCO_1P0, VAUXV-
CO_1P0, VCONV_1P0, and VDIG_0P9 pins. Place these capacitors as close as possible to the device with the ground side of the bypass
capacitor placed so that ground currents flow away from other power pins and their bypass capacitors, if at all possible.
In a scenario when power supply follows the recommendations in
use), 4.7 μF capacitors at VRX2LO_1P0 and VRX1LO_1P0 pins are not necessary. The 1.0 V domains connected to the VRFLO1_1P0 and
VRFLO2_1P0 pins require 1 μF capacitors.
Signals with Lowest Routing Priority
The following guidelines govern the signals with the lowest signal routing priority. Route these after all critical signal routes are completed so
they do not interfere with the critical component placement and routing. Route the signals shown in
Connect a 4.99 kΩ resistor to the RBIAS pin (C14). This resistor must have a 1% tolerance or better.
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The device supports joint test action group (JTAG) boundary scan, and the MODE pin is used to access the function. Connect the MODE pin
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(L13) to ground for normal operation. Refer to the data sheet for JTAG boundary scan information.
Connect the RESETB pin (K13) to VDIGIO_1P8 with a 10 kΩ resistor for normal operation. Reset the device by driving this pin low.
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When routing digital signals from rows K and below, it is important to route them away from the analog section (rows A through H). The
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digital-signal routing should not pass above the red dotted line highlighted in
Route the AGPIO_N signals using inner PCB layers. These signals control the analog blocks such as power amplifiers or low-noise
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amplifiers. Also use the AGPIO_0 through AGPIO_3 as general-purpose analog outputs when muxed with the internal AUXDAC outputs. To
prevent noise coupling into these signals, route them away from the digital region (above the red dotted line highlighted in
Route the AuxADC_N signals using inner PCB layers. These signals sense the analog voltage levels such as temperature sensors. To
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prevent noise coupling into these signals, route them away from the digital region (above the red dotted line highlighted in
The MODEA signal sets up the operation of the DEV_CLK_IN ± pins (LVDS differential, CMOS single-ended, XTAL with different bias
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voltage). Follow the recommendations in the
The MCS± signals are treated as differential. If using the multichip synchronization feature in the end application, route these signals with
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traces matching the length of the DEV_CLK_IN ± traces.
analog.com
Figure 257 (some internal LDOs bypassed, external 1.0 V analog domain in
Connection for External Device Clock (DEV_CLK_IN)
Figure 258
Figure 258.
section when controlling this pin.
ADRV9001
with the lowest priority.
Figure 258).
Figure 258).
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