Synthesizer Configuration And Lo Operation; Clock Synthesizer; Rf Synthesizer - Analog Devices ADRV9001 User Manual

Reference Manual ADRV9001

SYNTHESIZER CONFIGURATION AND LO OPERATION

The ADRV9001 family devices employ four PLL synthesizers: clock, RF (×2), and auxiliary. Each PLL is based on a fractional-N architecture
and consists of a common block made up of a reference clock divider, phase frequency detector, charge pump, loop filter, feedback divider,
digital control block, and either a 1 or 4 core voltage-controlled oscillator (VCO). The VCO has a tuning range of 6.5 GHz to 13 GHz. Each
PLL drives its own LO generator: RF LOGEN, aux LOGEN, and CLKGEN. The output of the LOGEN block is a divided version of the VCO
frequency. No external components are required to cover the entire frequency range of the device. The reference frequency for the PLL is
scaled from the reference clock applied to the device. Figure 93 shows the synthesizer interconnection and clock/LO distribution block diagram.
Figure 93. Synthesizer Interconnection and Clock/LO Distribution Block Diagram
Each receiver channel is used as an ORx for transmitter channels, as shown in Figure 94.
Figure 94. Synthesizer Interconnection and Clock/LO Distribution Diagram (Receiver Channels Configured as Observation Receivers for Transmitter Channels)

CLOCK SYNTHESIZER

The clock synthesizer generates all the clocking signals necessary to run the device. The synthesizer uses a single core VCO block. The
reference frequency for the clock PLL is scaled from the device clock by the reference clock generator. Reconfiguration of the clock synthesizer
is typically not necessary after initialization. The most direct approach to configure is to follow the recommended programming sequence
and use the provided API functions to set the clock synthesizer to the desired mode of operation. The clock generation block of the clock
synthesizer provides clock signals for the high speed digital clock, receiver ADC sample and interface clocks, transmitter DAC sample and
interface clocks, and LVDS interface clocks.
There are two types of clock synthesizers for the digital clock generation. For more details, see the Clock Generation section.

RF SYNTHESIZER

The device contains two RF PLLs. Each RF PLL uses the PLL block common to all synthesizers in the device and employs a four core VCO
block, which provides a 6 dB phase noise improvement over the single core VCO. As with the other synthesizers in the device, the reference
for RF PLL 1 and RF PLL 2 are sourced from the reference generation block of the device. The RF PLLs are also fractional-N architectures
with a programmable modulus. The default modulus of 8,388,593 is programmed to provide an exact frequency on at least a 5 kHz raster using
certain reference clocks, which are integer multiples of 38.40 MHz. The RF LO frequency is derived by dividing down the VCO output in the
LOGEN block. The tunable range of the RF LO is 30 MHz to 6000 MHz.
A switching network is implemented in the device to provide flexibility in LO assignment for the two RF LO sources. Figure 95 and Figure 96
show the switching network.
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