Gain Control Detectors - Analog Devices ADRV9001 User Manual

Reference Manual
RECEIVER GAIN CONTROL
consecutive DGPIO pins should always be configured as a pair to retrieve two consecutive bitfields (Bit 0 and Bit 1 or Bit 2 and Bit 3 in both
modes). The following enum type defines the DGPIO pin selection.
typedef enum adi_adrv9001_GpioPinCrumbSel
{
ADI__GPIO_PIN_CRUMB_UNASSIGNED,
ADI__GPIO_PIN_CRUMB_01_00,
ADI__GPIO_PIN_CRUMB_03_02,
ADI__GPIO_PIN_CRUMB_05_04,
ADI__GPIO_PIN_CRUMB_07_06,
ADI__GPIO_PIN_CRUMB_09_08,
ADI__GPIO_PIN_CRUMB_11_10,
ADI__GPIO_PIN_CRUMB_13_12,
ADI__GPIO_PIN_CRUMB_15_14,
} adi_adrv9001_GpioPinCrumbSel_e
In both the peak and peak/power modes, a pair of bits (Bit 0 and Bit 1 or Bit 2 and Bit 3) can choose any one pair of GPIO pins defined in
"adi_adrv9001_GpioPinCrumbSel_e". If "ADI_ADRV9001_GPIO_PIN_CRUMB_UNASSIGNED" is selected, it means that no GPIO pins are
assigned. So, the corresponding bitfields cannot be observed. The DGPIO pins are associated with either one of the receivers.
Table 76. DGPIO Configuration for Retrieving Signal Detector Information
Mode Bit Field Definition
Peak Mode hb_low_threshold_counter_exceeded (low threshold (hbUnderRangeHighThresh) is exceeded counter times, no
underload condition)
apd_low_threshold_counter_exceeded (low threshold is exceeded counter times, no underload condition)
hb_high_threshold_counter_exceeded (high threshold is exceeded counter times, overload condition)
apd_high_threshold_counter_exceeded (high threshold is exceeded counter times, overload condition)
Peak and Power Mode power_inner_low_threshold_exceeded (inner low threshold exceeded, no underload condition)
power_inner_high_threshold_exceeded (inner high threshold exceeded, overload condition)
apd_low_threshold_counter_exceeded (low threshold is exceeded counter times, no underload condition)
apd_high_threshold_counter_exceeded (high threshold is exceeded counter times, overload condition)
As mentioned earlier, the status of signal detectors can also be retrieved in the AGC mode. Note that the signal detector status does not always
correspond to the final AGC decision for gain increment or decrement, particularly due to the mitigation mode, in which the user can observe
the APD high threshold exceeded, but no gain change happens as the secondary digital threshold helps to detect the false positive of the APD,
which is caused by the near DC low frequency signal.

GAIN CONTROL DETECTORS

This section discusses three gain control detectors in more details.
Analog Peak Detector (APD)
The analog peak detector is located in the analog domain following the TIA filter and before the ADC input. It functions by comparing the signal
level to programmable thresholds. When a threshold is exceeded a programmable number of times in a gain update period, the detector flags
an overrange condition.
analog.com
ADRV9001
Feedback Mask Bit Position
0
1
2
3
0
1
2
3
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