Power-Down/Up Channel In Calibrated State; Dynamic Interframe Power Saving - Analog Devices ADRV9001 User Manual

Reference Manual
POWER SAVING AND MONITOR MODE
Table 88. Power-Down Modes and Related Power-Down Components (Continued)
1, 2
Approximate Power-Up Time (μs)
3, 2
Approximate Power-Up Time (μs)
1
RF PLL is in normal calibration mode, power up time varies with DEV_CLK frequency.
2
At 184.32MHz processor clock
3
RF PLL is in fast calibration mode, power up time varies with DEV_CLK frequency.
Power-down mode 0 is the default power saving if power-saving API is not called to set other values. In this mode, the TX/RX enable pin
►
can automatically trigger powering up/down the TX/RX analog and digital datapath components such as mixer, A/D, filters, and so on. The
transition time is very short (around 4.5 µs).
Power-down mode 1 powers down internal RF PLLs in addition to mode 0 power down. After powering up, PLL requires recalibration. So, it
►
takes more time to power up.
Power-down mode 2 powers down some LDOs related to channels and RF PLLs in addition to mode 1 power down.
►
Power-down mode 3 powers down the TX/RX channels and PLLs (clock PLL, RF PLLs) only. No LDOs are powered down.
►
Power-down mode 4 powers down clock PLL and system LDOs related to TX/RX channels in addition to mode 3 power down.
►
Power-down mode 5 powers down almost the whole ADRV9001 chip, including ARM and memory, except for some wake-up circuits.
►

POWER-DOWN/UP CHANNEL IN CALIBRATED STATE

Dynamically power down/up individual channels (TX1/TX2/RX1/RX2) in the calibrated State if these channels are statically enabled in
the device profile. Call adi_adrv9001_Radio_Channel_PowerDown() to power down the specified channel, and it powers down the
channel-related LDOs and PLL for the channel in addition to the datapath power down. adi_adrv9001_Radio_Channel_PowerUp() powers up
the specified channel. The two APIs can only be called in the calibrated state.
Figure 180 shows a DMR radio switch from transmitter-only frames into transmitter/receiver alternate frames. The ADRV9001 is initialized with
the transmitter, and the receiver is enabled at the beginning of the transmitter-only frames. The baseband processor can bring the receiver
channel into the calibrated state and power it down. Then, before the transition of the TX/RX alternate frames, the baseband processor
can power up the receiver and move it into a primed state. The power saving of the transmitter channel in the gray area is addressed by
power-down modes discussed in the following sections.
Another use case example is if four channels ((TX1/TX2/RX1/RX2) are enabled in the profile, the unused channels can be temporarily powered
down by moving them to the calibrated state.

DYNAMIC INTERFRAME POWER SAVING

Dynamic interframe power saving runs automatically during all regular TDD transmitter/receiver operations. A higher level power-down mode
can be configured to get more power saving if the application has a longer transmitter/receiver transition time. DGPIO pins can be configured to
support additional power savings.
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Power-Down Modes
ARM (+ memories)
DEV_CLK = 30Mhz
DEV_CLK = 50Mhz
DEV_CLK = 100Mhz
DEV_CLK = 30Mhz
DEV_CLK = 50Mhz
DEV_CLK = 100Mhz
Figure 180. DMR Typical State Transition
0 (Default) 1 2
4.5 350 500
180 380
170 370
100 300
60 260
40 240
ADRV9001
3 4 5
x
250 650 3200
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