Analog Devices ADRV9001 User Manual page 300

Reference Manual
LDO CONFIGURATIONS
Table 122. LDO Mode for Power-Saving Configurations
Enumerator
ADI_ADRV9001_LDO_POWER_SAVING_MODE_1
ADI_ADRV9001_LDO_POWER_SAVING_MODE_2
ADI_ADRV9001_LDO_POWER_SAVING_MODE_3
ADI_ADRV9001_LDO_POWER_SAVING_MODE_4
ADI_ADRV9001_LDO_POWER_SAVING_MODE_5
LDO mode 1 (normal operation): The LDO is in a normal mode of operation. It is used to generate an on-chip voltage.
►
LDO mode 2 (LDO always off through PCB wiring): An LDO is not required and is permanently powered down through shorting its input pin,
►
and its output pin (if available) to ground on the PCB. Generally, use this mode if the entire power domain is not required. No software control
of the LDO is available.
LDO mode 3 (LDO always off through software): Use this for the various LDOs that do not have a physical output pin. These LDOs cannot
►
be physically tied to GND or bypassed as a result. use it if the LDOs with no output pin must be turned off. See
the LDOs.
LDO mode 5 (LDO in bypass mode): An LDO is not required and is placed into bypass mode through software control. However, the power
►
domain is still required. Apply a high-efficiency power source at the input pin. This mode allows to use higher efficiency power sources to
supply the ADRV9001, as opposed to having the power overhead associated with an LDO.
Table 123 lists each of the 19 LDOs as well as the constraints to explain when to power on/off, or bypass each LDO.
►
Table 123. LDO Constraints
Index LDO
0 GP_LDO_1
1 DEV_CLK_LDO
2 CONVERTER_LDO
3 RX_1_LO_LDO
4 TX_1_LO_LDO
5 GP_LDO_2
6 RX_2_LO_LDO
7 TX_2_LO_LDO
8 CLK_PLL_SYNTH_LDO
9 CLK_PLL_VCO_LDO
10 CLK_PLL_LP_SYNTH_LDO
11 CLK_PLL_LP_VCO_LDO
12 LO1_PLL_SYNTH_LDO
13 LO1_PLL_VCO_LDO
14 LO2_PLL_SYNTH_LDO
15 LO2_PLL_VCO_LDO
16 AUX_PLL_SYNTH_LDO
17 AUX_PLL_VCO_LDO
18 SRAM_LDO
Set up the three different configurations, as shown in
Table 124. Power-Saving Configuration for Each LDO
Index LDO
0 GP_LDO_1
1 DEV_CLK_LDO
2 CONVERTER_LDO
3 RX_1_LO_LDO
4 TX_1_LO_LDO
analog.com
Normal LDO operation.
LDO always off. Input and output of the LDO connected to ground. Used when a power domain is not required.
LDO always off through software.
Not used.
LDO bypassed. Supply an external source at the level expected at the LDO output (1 V, low noise, 2.5%
tolerance).
Constraints
Do not power down or bypass.
Do not power down or bypass.
Power down only if all ADCs and DACs must be powered down.
Power down if RX1 is not needed.
Power down if TX1 is not needed.
Do not bypass.
Power down if RX2 is not needed.
Power down if TX2 is not needed.
Power down if the CLK_PLL_LP is in use.
Power down if the CLK_PLL_LP is in use.
Power down if the CLK_PLL is in use.
Power down if the CLK_PLL is in use.
Power down if LO1 is being externally supplied.
Power down if LO1 is being externally supplied.
Power down if LO2 is being externally supplied.
Power down if LO2 is being externally supplied.
Power down if the AUX_PLL is not required.
Power down if the AUX_PLL is not required.
Do not power down or bypass.
Figure 279, in this function by setting the LDO modes per
Configuration 2
1
1
5
5
5
Table 123
Input Pin
VANA1_1P3
VANA2_1P3
VCONV_1P3
VRX1LO_1P3
VTX1LO_1P3
VANA2_1P3
VRX2LO_1P3
VTX2LO_1P3
VCLKSYN_1P3
VCLKVCO_1P3
VCLKSYN_1P3
VCLKVCO_1P3
VRFSYN1_1P3
VRFVCO1_1P3
VRFSYN2_1P3
VRFVCO2_1P3
VAXUSYN_1P3
VAUXVCO_1P3
VDIG_1P0
Table 124
Configuration 1
1
1
5
5
5
ADRV9001
for the details of
Output Pin
VANA1_1P0
VANA2_1P0
VCONV_1P0
VRX1LO_1P0
VTX1LO_1P0
VANA2_1P0
VRX2LO_1P0
VTX2LO_1P0
N/A
VCLKVCO_1P0
N/A
VCLKVCO_1P0
N/A
VRFVCO1_1P0
N/A
VRFVCO2_1P0
N/A
VAUXVCO_1P0
VDIG_0P9
and Table 123 .
Configuration 0
1
1
1
1
1
Rev. 0 | 300 of 351