Digital Front End (Dfe) - Analog Devices ADRV9001 User Manual

Reference Manual
TRANSMITTER SIGNAL CHAIN
by two interpolation stages through a flexible combination of interpolation filters. The interpolation ratios and filters are controlled by the profiles.
By design, the interpolation images are rejected by more than 110 dB. Between the two interpolation stages, there is an optional FM/FSK
modulator called IQ FM/FSK and a digital upconverter (DUC), which can both be bypassed. Finally, for IQ data, the signal is interpolated to the
DAC sample rate.
Figure 127 shows that the DFE subsystem also includes various signal conditioning algorithms, such as LOL suppression and quadrature error
correction (QEC). Besides these, it also provides power amplifier protection and transmitter attenuation control blocks.
The output of the DFE is sent through the DAC in the AFE subsystem. The DAC standard clock rate can be programmed to be 184.32, 368.64,
or 552.96 MHz, which is set by the profile. (Note that other sample rates can also be supported when an arbitrary sample rate is employed.)
Then, the DAC output is filtered by the LPF and input to the upconversion mixer.
Figure 127 shows that the ADRV9001 device also supports another method of FM/FSK modulation called Direct FM/FSK modulation. In this
mode, the DUC, IQ FM/FSK, the interpolation stage 2, power amplifier protection, and transmitter attenuation blocks (digital part) are all
bypassed. RFPLL is used to generate a constant envelope phase-modulated signal by modulating the sigma-delta modulator (SDM) with the
data stream. In Direct FM/FSK, both the DAC and LPF can be powered down.
The following subsections discuss the major transmitter functionalities.

DIGITAL FRONT END (DFE)

Programmable FIR Filter (PFIR)
The PFIR has 128 taps with 24-bit coefficients. There are two FIR filters (PFIR_I and PFIR_Q), as shown in
operate in parallel, one for I data and one for Q data in digital IQ modulation applications such as long-term evolution (LTE). It can also
be configured to use PFIR_I or PFIR_Q only or to operate both filters sequentially for FM/FSK applications. Optionally, use this PFIR for
applications by loading a set of PFIR coefficients.
Before this PFIR, there is also an option to perform interpolation with the interpolation factor of 1 and 2. In such a case, design the PFIR
for filtering after interpolation. For unity gain, calculate the PFIR coefficients scaling factor as 2 ^ 23 * Interpolation_factor/(sum of the filter
coefficients). If fewer than 128 coefficients are specified, append the zeros.
Transmit Attenuation Control
Transmit Gain Table
The transmitter attenuation block controls the transmitter output power. A transmitter gain table with 960 entries is loaded into the ADRV9001's
memory during initialization. Currently, only the first 840 entries are used. Each entry equals a 0.05 dB gain step. Therefore, there is a total gain
range of 42 dB. The total transmitter attenuation is distributed into two portions, an analog attenuation portion and a digital attenuation portion.
In the analog attenuation, there is a digitally controlled step attenuator (DSA) with 64 unit steps on a linear scale. The gaps between the analog
gain steps are interpolated by a 12-bit digital multiplier to 0.05 dB steps. The maximum analog attenuation is 36 dB, and the maximum digital
attenuation is 6 dB. Note in the direct FM/FSK mode, the maximum transmitter attenuation is 12 dB with 0.5 dB step size.
Table 57 shows the first five rows of the transmitter gain table.
Table 57. Sample Rows from the Tx Gain Table
Transmitter Total Transmitter
Attenuation Index Attenuation (dB)
0 0
1 0.05
2 0.10
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Figure 128. Programmable FIR Filters
Analog Attenuation Analog Attenuation
Control Word[5:0] (dB)
0 0.00
0 0.00
0 0.00
Figure
Digital Attenuation Digital Attenuation
(dB) (Linear)
0.00 1.00
0.05 0.9943
0.10 0.9886
ADRV9001
128. It is configured to
Digital Attenuation
Control Word[11:0]
4095
4072
4049
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