Analog Devices ADRV9001 User Manual page 67

Reference Manual
DATA INTERFACE
Figure 48 shows the transmit CMOS SSI with DDR clock in relation to the strobe/data, with respect to the ADRV9001. Each edge of the clock
(positive and negative) samples the corresponding strobe/data sample based on the interface setup/hold timing.
When the baseband processor drives out the transmit SSI clock, strobe, and data to the ADRV9001, the output DDR clock can either be
in-phase with the strobe/data or delayed by a quarter cycle of the clock period. Regardless of the choice, the relationship between the transmit
DDR clock and strobe/data must meet the ADRV9001 setup and hold timing specification.
Figure 49 and Figure 50 show the timing diagram examples for four-lane mode receive and transmit CSSI with DDR clock and 16-bit I/Q
samples.
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Figure 47. Receive CSSI DDR Clock Relation with Strobe/Data
Figure 48. Transmit CSSI DDR Clock Relation with Strobe/Data
Figure 49. Four-Lane Mode Receive CSSI DDR Timing for 16-Bit I/Q Data Sample
ADRV9001
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