Analog Front-End Components - Analog Devices ADRV9001 User Manual

Reference Manual ADRV9001
RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN
Figure 137. Rx Signal Chain Block Diagram
The ADRV9001 supports three standard ADC clocks: ADC-H clock 2211.84 MHz, ADC-M clock 1474.56 MHz, and ADC-L clock 1105.92 MHz
for both HP ADC and LP ADC (note that the ADC clock varies with arbitrary sample rate.). In the DFE subsystem, the ADC output signals at
three different sample rates go through two decimation stages, as shown in Figure 137, to convert to the desired sample rate by using a flexible
combination of decimators. Between the two decimation stages, there is an optional DDC, which is employed in the applications, and which
adopts IF reception scheme.
At different decimation stages, several signal conditioning algorithms are performed, which are overload detection for gain control, DC offset
correction (DC), and QEC, as shown in Figure 137. The overload detection result is used by the AGC or manual gain control (MGC) algorithms
to properly control both analog and digital gain through a receiver gain table. The analog gain is applied at the front-end attenuator to
avoid overload/underload situations. The digital gain is applied at the gain compensation block in the receiver datapath and it has two major
functionalities: one is to correct the small step size inaccuracy of the front end analog gain and the other is to compensate for the front end gain
change completely so that it is transparent to users. The different receiver gain tables are loaded for either correction or compensation based
on the user's configuration during the device initialization. In the ADRV9001, there is a sophisticated gain control mechanism (AGC/MGC). For
more details, see the Receiver Gain Control section. The DC and QEC are used to correct the DC offset and quadrature error, so that the signal
distortion is minimized to achieve an optimal performance before sending data to the baseband processor. To achieve the best performance for
different applications, QEC algorithm is designed differently for WB and NB applications.
After decimation stage two, the ADRV9001 provides an option to correct the small carrier frequency offset through API commands, followed by
a 128-tap programmable PFIR as a channel selection filter.
After PFIR, besides applying the digital gain as discussed, apply an interface gain optionally using the signal strength measurement
from the RSSI. Apply the interface gain through a "Slicer" by properly shifting the signal. When the signal is large, it is used to avoid
saturating the data port due to a limited bit-width, and when the signal is small, it is used to avoid losing sensitivity. An API command
adi_adrv9001_Rx_Rssi_Read() reads the signal strength measurement. Apply the interface gain automatically in the device or manually
through API commands. This is beneficial when there is saturation in the baseband processor. For more details, see the Receiver Gain Control
section.
The RSSI is also used as the signal detector in the receiver Monitor Mode. In NB applications, at the end of the datapath, the device provides
an option to discriminate the FSK frequency shift and, in addition, detect the DMR sync patterns, which is critical for the receiver Monitor Mode.
Note that there is phase offset correction capability at the end of the receiver datapath to ensure the signal fidelity. Finally, the output signal is
sent through the CMOS-SSI/LVDS-SSI data port to the baseband processor for further processing.

ANALOG FRONT-END COMPONENTS

Analog Front Attenuator
The analog front attenuator is a PI resistive network that provides a constant 100 Ω differential input impedance with the passive mixer.
The gain control functionality controls it in the receive datapath to adjust the signal gain to avoid overloading the datapath through overload
detectors. When there is a strong interferer, the gain is decreased and when the interferer disappears, the gain is increased, so that the desired
signal level is adjusted back to the proper level.
The attenuator has 256 gain settings providing a receiver attenuation range from 0 to 20 × log(1/256) = -48 dB. Typically, only a subset of this
range is used. In the ADRV9001, the current range of the attenuation is from 0 to -34 dB. Calculate the gain of the attenuator by the following
equation:
256 − fe_gain_cw[7: 0]
256
ATTEN = 20 × log10
dB
analog.com Rev. 0 | 141 of 351