Analog Devices ADRV9001 User Manual page 62

Reference Manual
DATA INTERFACE
For I data duration and low for Q data duration. For a 16-bit data sample, RX_STROBE is high for 16 clock cycles (I data sample) and low for
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16 clock cycles (Q data sample).
Transmit CSSI
The one-lane mode transmits the CSSI of each channel (Tx1 and Tx2). This is a 4-wire digital interface consisting of:
TX_DCLK_IN: input clock synchronized to the data and strobe inputs.
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TX_STROBE_IN: input signal indicating the first bit of the serial data sample.
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TX_DATA_IN: input serial data stream.
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TX_DCLK_OUT: optional output reference clock provided to the baseband processor to generate all the signals shown in
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baseband processor can also use RX_DCLK_OUT as the reference clock when its clock rate is equal with the Transmit SSI clock rate.
The I and Q samples can be deserialized, starting with configurable I or Q first and MSB or LSB first.
and Tx2) for a 16-bit I/Q data sample with I sample and MSB first configuration.
The TX_STROBE_IN signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high:
For one clock cycle at the start of I and Q sample transmit. For a 16-bit data sample, the TX_STROBE is high for one clock cycle and low for
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31 clock cycles.
For I data duration and low for Q data duration. For a 16-bit data sample, TX_STROBE is high for 16 clock cycles (I data sample) and low for
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16 clock cycles (Q data sample).
CSSI Data Symbols Transmit and Receive
The previous sections describe data transfer with I/Q format with 16-bit width. When the ADRV9001 internal modulation/demodulation is
enabled (see the Transmitter Signal Chain
processor is 2 bits or 16 bits I only data (denoted as symbol to differentiate with I/Q complex samples). In a symbol format mode, raw data is
transferred through this interface using different data sizes. The CSSI interface supports three additional data formats:
2 bits of data
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8 bits of data
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16 bits of data
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Two bits of data can be transferred over a CSSI with an 8-bit data format with six dummy bits. The clock and strobe behavior are similar to the
I/Q format described in the previous sections.
Figure 33 shows the receive CSSI (Rx) for 2-bit data symbols.
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Figure 32. Transmit CSSI Timing for 16-Bit I/Q Data Sample (I and MSB First)
and Receiver Demodulator sections), the data transfer between the ADRV9001 and baseband
ADRV9001
Figure
Figure 32 shows the transmit CSSI (Tx1
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32. The