Analog Devices ADAV4601 System Design Document
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Analog Devices ADAV4601 System Design Document

Analog Devices ADAV4601 System Design Document

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ADAV4601 System Design Document Rev. 1
ADAV4601 System Design Document
Rev.1 August 2009
Analog Devices
Confidential Information
Page 1

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Summary of Contents for Analog Devices ADAV4601

  • Page 1 ADAV4601 System Design Document Rev. 1 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 1...

  • Page 2: Table Of Contents

    Providing a Clock Source for the ADAV4601 ...........................8 Clocking the ADAV4601 using the onboard crystal (Y3)......................9 Clocking the ADAV4601 using the 96-Way Connector (MCLK) ....................10 Clocking the ADAV4601 using the 96-Way Connector (BCLK1) ..................... 11 Evaluation Board I/O .................................... 12 Analog I/O .......................................
  • Page 3 Address 0x011C and Address 0x011D Headphone 1/AUXOUT4 Right Balance Control Registers (Default: 0x0080, 0x0000) ....................................82 Address 0x011E and Address 0x011F Headphone 1/AUXOUT4 Volume Control Registers (Default: 0x0080, 0x0000)....................................... 82 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices...
  • Page 4 Appendix B – Layout Recommendations ..................99 Decoupling......................................99 Crystal Oscillator Circuit ..................................99 PWM Outputs ....................................... 100 Ground Plane......................................100 Appendix C – ADAV4601 Bill of Materials................... 101 Appendix D – Schematics ........................ 107 ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 5: Introduction

    INTRODUCTION The purpose of this document is to help with the design in of the ADAV4601 into a system. The document is detailed as follows Section 1 – Getting the Evaluation Board Up and Running • Outlines the ADAV4601 evaluation board. Gives a brief description of the ways in which the evaluation board and the ADAV4601 can be configured.

  • Page 6: Section 1 - Getting The Evaluation Board Up And Running

    ADAV4601 evaluation board and also the ways in which data can be passed to and taken from the ADAV4601 as well as the several ways in which the device can be clocked. Figure 1 indicates the various sections on the evaluation board.

  • Page 7: Evaluation Board Description

    EVALUATION BOARD DESCRIPTION The Evaluation board allows the flexible testing of the ADAV4601 audio processor. Both analog and digital I/O can be handled. The various connectors are listed below. Table 1 Evaluation Board Connectors Connector Name Function 7.5V DC Power supply...

  • Page 8: Adav4601 Evaluation Board Quick Start

    The ADAV4601 contains a phase-locked loop (PLL) that generates all of the internal clocks required by the ADAV4601. It is possible to set the master clock (MCLK) frequency to be 64*Fs, 128*Fs, 256*Fs or 512*Fs, where Fs is the sampling frequency and is set at 48 kHz. The ADAV4601 Evaluation Board therefore requires a clock source and there are a number of ways in which to provide this.

  • Page 9: Clocking The Adav4601 Using The Onboard Crystal (Y3)

    CLOCKING THE ADAV4601 USING THE ONBOARD CRYSTAL (Y3) a) To enable the onboard crystal (Y3) to clock the ADAV4601, jumper 12 (J12) must be set to position 4-3. If the user wants to use digital data from the SPDIF receiver in this mode, the data will not be synchronous to the master clock and is therefore handled by the SRC1 of the ADAV4601.

  • Page 10: Clocking The Adav4601 Using The 96-Way Connector (Mclk)

    CLOCKING THE ADAV4601 USING THE 96-WAY CONNECTOR (MCLK) b) To clock the ADAV4601 using the MCLK from the 96-way connector, jumper 12 (J12) must be set to position 1-4. Data from the 96-way connector in this mode can be synchronous or asynchronous, if there is data is from the SPDIF connector this is asynchronous and can be handled using the SRC1.

  • Page 11: Clocking The Adav4601 Using The 96-Way Connector (Bclk1)

    CLOCKING THE ADAV4601 USING THE 96-WAY CONNECTOR (BCLK1) c) To clock the ADAV4601 using the BCLK1 from the 96 way connector, jumper 12 (J12) must be set to position 2-4. Data from the 96 way connector in this mode can be synchronous or asynchronous, if there is data is from the SPDIF connector this is asynchronous and can be handled using the SRC1.

  • Page 12: Evaluation Board I/O

    When valid data is decoded by the SPDIF receiver, the data is automatically passed through to the SRC1 of the ADAV4601 and is handled as asynchronous data. The reason this data is handled by the SRC is due to the fact that the received data is not synchronised to the MCLK of the ADAV4601 and must be re-synchronised to the internal processor.

  • Page 13: Pwm Outputs

    PWM OUTPUTS Figure 6: PWM Outputs The differential PWM outputs from the ADAV4601 are available on header J6 for connection to a Class-D power stage. Table 3: PWM OUT Signals on J6 Signal PWM4B PWM4A PWM3B PWM3A PWM2B PWM2A PWM1B...

  • Page 14: Testpoints

    Pin 35 of DUT (Not Stuffed) TP36 LRCLK1 Pin 36 of DUT (Not Stuffed) TP37 Pin 37 of DUT – I C Address select on reset (Not Stuffed) TP42 DGND TP43 DGND ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 14...

  • Page 15: Section 2 - Powering Up The Adav4601

    MCLKI frequency is set to be 24.576Mhz. Depending on the clock frequency required, this register must be set accordingly. 34 0006 0200 This register write powers up the PLL block in the ADAV4601. This bit must be set to ensure the correct operation of the device. 34 000A 0801 Setting this register to this enables the PLL for use.
  • Page 16 Note: AUXDAC4 and headphone 1 are connected together. Therefore, to use AUXDAC4, headphone 1 must be powered up. Note: Theses two writes power up all available DACs on the ADAV4601. In power critical applications or depending on the number of DACs required, the user can power up the minimum number of DACs needed for operation.
  • Page 17 34 0000 001B This register write now enables the Audio Processor for the ADAV4601. It also globally powers up all parts of the ADAV4601 that have not already been powered up, this will include the SRCs, the PWM section, the ADC and DAC engine (as well as all the ADCs which had not been previously powered up) and the audio processor.
  • Page 18 Note: This register write powers up all parts of the ADAV4601 that were not previously powered up. In power critical applications this may not be desired. In this case the ADAV4601 can have the various digital blocks powered up individually using the digital power management register.
  • Page 19 This register is the PWM control register 2. By setting this register to this value, the PWM outputs are re-synced at the output pads by a clock from the digital core of the ADAV46xx. By default all 4 PWM outputs from the ADAV4601 are phase shifted by 45°.
  • Page 20 34 0121 00FF This register write, un-mutes the ADAV4601. If the there is data on the SRC1 channel this should now be available on all outputs. ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 21: Power Down Sequence

    Note: By default this power up sequence puts data from SRC1 out on all outputs of the ADAV4601. This will have to be changed depending on the flow used. POWER DOWN SEQUENCE From the powered up state that was described in the previous section. The following is the recommended sequence when powering down the ADAV4601.
  • Page 22 34 0000 0000 This register write powers down the rest of the device. This disables all the digital section on the ADAV46xx as well as disabling the processor and the PLL. ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 23: Section 3 - Programming The Adav4601

    SECTION 3 – PROGRAMMING THE ADAV4601 DESIGNING AND DEVELOPING This section describes how it is possible to control the ADAV4601 audio processor and evaluation board with the software supplied. If the customer wishes to develop their own custom audio flow. Analog Devices, Inc. offers an award-winning graphical programming tool (SigmaStudio™) that allows custom flows to be quickly developed and evaluated.

  • Page 24: Connecting The Hardware

    CONNECTING THE HARDWARE The ADAV4601 evaluation kit ships with a USB to serial converter and adaptor board which allows the graphical programming suite SigmaStudio to communicate with the ADAV4601 evaluation board. The boards should be connected as shown in Figure 15. The SigmaStudio USB Serial converter and adaptor board should be connected to the ADAV4601 Evaluation board using the 96-way connector (J3).
  • Page 25 SigmaStudio Program. When this is opened the dlls that have been copied to the SigmaStudio directory on the C drive should be selected here. These dll files are now available to use in SigmaStudio. Figure 18: Add-Ins Browser ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices...

  • Page 26: Evaluating The Adav4601 Using Sigmastudio

    EVALUATING THE ADAV4601 USING SIGMASTUDIO An example SigmaStudio project is supplied with the ADAV4601 evaluation board. Once SigmaStudio has been launched, select File -> Open, and then navigate to the following folder C:\Program Files\Analog Devices\ADAV46xx Documentation\Sample Audio Flow. In this folder select the project files entitled, Sample Audio Flow.dspproj.

  • Page 27: Powering Up The Adav4601 Evaluation Board

    Note: This power up sequence is simply designed to power up and enable the audio processor. When designing the ADAV4601 into a system, it is recommended to use the power up sequence documented in Section 2 – Powering up the ADAV4601.

  • Page 28: Downloading And Compiling An Audio Flow

    DOWNLOADING AND COMPILING AN AUDIO FLOW Once the Audio Flow is created in SigmaStudio and the ADAV4601 is fully powered up, all that remains to be done is for the audio flow created in SigmaStudio to be compiled and downloaded.

  • Page 29: Creating A New Audio Flow

    Note: The green status bar only indicates if the audio flow has compiled properly, this is not an indication that the flow has downloaded properly to the ADAV4601, therefore it is important to read back from the registers when powering up the ADAV4601 to ensure that SigmaStudio is communicating properly with the USB adaptor board.
  • Page 30 The adaptor board should always be connected before SigmaStudio is launched. Figure 24: Connecting the Eval Board to the Adaptor Board SigmaStudio is now configured to use the ADAV4601 Evaluation Board. To begin creating a new flow click on the Schematic tab.
  • Page 31 In order to pass data from the various hardware blocks on the ADAV4601, such as ADCs, DACs and SRCs to the Audio flow, each input and output on the ADAV4601 has a input pin assignment in SigmaStudio. The pin assignments and how they correspond with the appropriate inputs and outputs is shown in Figure 27.
  • Page 32 ADAV4601 HPOUT1R HPOUT1R SYNCHRONOUS SYNCHRONOUS DELAY DELAY AUXOUT3L AUXOUT3L MEMORY MEMORY AUXOUT3R AUXOUT3R Figure 27: SigmaStudio IO Table 6: ADAV4601 SigmaStudio Pin Assigments Input Output Channels Channels SDINL0 SDOL0 SDINR0 SDOR0 SDINL1 2 – 7 No Connect SDINR1 PWM1/ AUXOUT3L...
  • Page 33 Note: An important point to note is that the size and functionality of the Audio Flow is limited by the number of instructions available in the Program ROM of the ADAV4601. This is only critical for very large designs so therefore care should be taken when designing large audio flows.

  • Page 34: Using Sigmastudio To Control The Default Audio Flow

    Figure 30: Default Audio Flow for the ADAV4601 The default audio flow in the ADAV4601 is a comprehensive solution which could be utilized in many TV applications. The flow incorporates full matrix switching (any input to any output) and offers a couple of different Analog Devices patented algorithms such as an AVC (Automatic Volume Control) and Spatializer.
  • Page 35 Figure 31: Power UpADAV4601.iic To Power Up the ADAV4601, select the Write button, this will write the power up sequence to the device. Once written, the values written can be read back using the Read button. This will return the following dialog box.
  • Page 36 This can then be written to the part as described previously. Likewise all other Default Audio Flow settings can be controlled in a similar way allowing the user full control. For more details on the default audio flow loaded in the ADAV4601, please refer to Appendix A – Detailed Register Descriptions for more details.

  • Page 37: Adav4Xxx Self Boot

    ADAV4601 SELF BOOT If a custom flow has been designed, it can be stored on an external EEPROM. The ADAV4601 features a self boot option which allows the part to copy ROMS from an EEPROM to its own internal memory. In this way, the user can develop their own custom flows and have them loaded to the ADAV4601 on start up.

  • Page 38: Boot Time

    Number of blocks to be read (addresses + data) (For example above, Length would be 0009h) Device Address: Chip Address of ADAV4601 Address: Target Memory address in ADAV4601 Data : Data to be written Message Byte: 0x01: Block Message Followed by data...
  • Page 39 The part should be muted for the duration of the transfer, to avoid unwanted noises on the output. Once the transfer of data is complete, the ADAV4601 returns to slave mode. The microcontroller can now access the I2C bus again and continue programming the ADAV4601 and other devices.

  • Page 40: Section 4 - The Default Flow

    0x0101 0x0103 0x0121 SDOL0 SDOR0 0x0101 0x0103 0x0121 Figure 34: Default Audio Flow for the ADAV4601 DEFAULT FLOW STRUCTURE The Default Flow consists of five parallel channels all of which are muted by default; Main Headphone AUXOUT1 S/PDIF SDO0 Main Channel The core of the Default Flow is the Main Channel which provides the main audio processing;...

  • Page 41: Headphone Channel

    34 0122 FDC1 #Enable AVC, Lip Sync, EQ, Bass, Loudness, Limiter, Crossover. 34 0122 FDE1 #Add the tweeter and woofer channels together 34 0121 0020 #Unmute Main Tweeter/AUXOUT3 output ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 41...
  • Page 42 #Unmute S/PDIF output Digital In (I S) to Analog Out with no audio processing 34 0101 0030 #Route SDIN0 to AUXOUT1 34 0121 0002 #Unmute AUXOUT1 output ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 42...

  • Page 43: Changing The Volume

    The volume works by multiplying the decimal contents of the volume control register by the signal. The volume control is a 28-bit word in 5.23 two’s complement format. The ADAV4601 uses 16-bit registers therefore the volume control must be spread over two registers. The figure below graphically illustrates how this is arranged.
  • Page 44 Then simply convert this 5.23 decimal number to Hexadecimal. 0x00FF64C1 Write this value to the registers. 34 0114 00FF64C1 The same idea applies to other 28-bit words that are spread over two registers. ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 44...

  • Page 45: Section 5 - Interfacing The Adav4601 To A System

    USING THE DEFAULT FLOW The ADAV4601 has a default audio flow on board and was previously shown in Figure 34. The register map for this flow is in the Default Audio Flow Registers section in Appendix A – Detailed Register Descriptions. The default flow is very simple to control requiring only one I C write to change parameters of filters, volumes, gains, etc.

  • Page 46: Custom Flow Example

    The system controller provides the filter coefficients, b , in 5.23 format. = 0.0156048536300659 -> 0x0001FF57 = 0.0312097072601318 -> 0x0003FEAE = 0.0156048536300659 -> 0x0001FF57 = 1.76945173740387 -> 0x00E27D65 = -0.831871271133423 -> 0x0F95853E ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 46...

  • Page 47: Roms And Registers

    34 0200 0010 ROMS and Registers When the ADAV4601 is configured for use with a custom flow it contains two ROMS: program and parameter. Both can be stored externally on an EEPROM and can be loaded after power-up. Program ROM Program ROM is 42-bits wide and occupies Address 0x1400 to Address 0x1FFF.

  • Page 48: Using A Custom Flow With The Application Layer

    C writes. ROMS and Registers When the ADAV4601 is configured for use with the Application Layer it contains four ROMS: program, instruction, parameter, and LUT. All can be stored externally on an EEPROM and can be loaded after power-up. Program ROM Program ROM is 42-bits wide and occupies Address 0x1400 to Address 0x1FFF.

  • Page 49: Adav4601 System Design Document Confidential Information

    Rather than ending the control port transaction (by issuing a stop command in I C mode), as would be done in a single-address write, the next data-word can be written immediately without specifying its address. ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 50: Section 6 - The Application Layer Creation Software

    The purpose of the Application Layer is to simplify system design and reduce time to market. It achieves this by drastically reducing I C writes while still maintaining full control over a customised audio flow in the ADAV4601. What this means to the user is the chance to have complicated functions in the audio flow and yet simple register writes to control these functions.

  • Page 51: Linking The Application Layer Software To Your Audio Flow

    Generate params.params file. Save it in /project_folder/IC1_name_of_folder Input “params” as file name. Save it in /project_folder/IC1_name_of_folder Figure 39:Generating and saving files for use in the Application Layer Software ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 51...

  • Page 52: Application Layer Software Gui

    APPLICATION LAYER SOFTWARE GUI To start the program, click Start -> All Programs -> Analog Devices -> Analog Devices Application Layer -> Application Layer. Once loaded, the software GUI looks like Figure 40 below. For more information about each function, please refer to the User Manual section.

  • Page 53: User Manual

    Loads a previous project from disk. Application Layer GUI project files have the .grp extension. Select .grp file and click OK Figure 43: Load project Save All Saves current project to disk (auto-save mode by default). Quit Exits from the application. ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 53...

  • Page 54: Compile And Download

    No registers defined: the project is blank, no registers have been created. • Files missing. Please import SigmaStudio project to flow: the SigmaStudio set of files is missing, please • import them as shown in Figure 46. ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 54...

  • Page 55: Import Sigmastudio

    Application Layer when is written to. Register name, and input names, are given by the user when creating the register map. Register name, address and default value. 16 bits per register Input “FREQ” bits 9 to 12. Figure 47 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 55...

  • Page 56: Sigmastudio Cells And Cell Parameters

    This should be only done for development and debug purposes, and is not supported from the Application Layer GUI. Parameter Name: Name of the selected parameter. ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 57: Path Information

    16 bits per register. By default, the new register number will be the lowest available, and it's assigned automatically. It can be changed, see the Edit Register section for more information about the registers structure, see Application Layer Register Structure section. ADAV4601 System Design Document Confidential Information Rev.1 August 2009...
  • Page 58 16. Depending on the configuration of the cell control, the number of bits needed, will change. The wizard will know how many bits are available for the input to be created, and in case it doesn't fit it will show an error. ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 59: Edit Register

    Each register has a register name, and a register number. The numbers are automatically assigned (lowest available), and can be changed as described in the last section. ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 60: Editing A Cell Previously Defined

    “UNASSIGNED” means the field is unused. Click a register in the Register list and it will display it automatically. 1) Field Names 2) Default bit values Figure 58: Register information window ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 60...

  • Page 61: The Cell Wizards

    Note: When selecting the volume or gain block in SigmaStudio, choose the shared volume control. This uses a single parameter for the volume control. This is more efficient and easier to control using the Application Layer. The other volume controls are not supported. ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 62: Filters Wizard

    A filter controlled by frequency will have all the gain related parameters fixed. Writing to the cut off frequency value field, the cut off frequency response of the filter will change. Figure 62: Filter control for Frequency (Hz) ADAV4601 System Design Document Confidential Information Rev.1 August 2009...

  • Page 63: Filter Type Selection

    3) Leave the default value highlighted Figure 64: Muxes wizard Delay Wizard Figure 65: Delay wizard The delay wizard creates a single or multiple delay block control. ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 63...

  • Page 64: Loudness Wizard

    1) If ticked, a 0 will mute the output. If unticked a 1 will mute the output. 2) If ticked, by default the block will be muted Figure 68: Mute wizard ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 64...

  • Page 65: Enable Wizard

    Figure 70: Import Wizard (1) 1) Input register name 2) Select input name (Internal use only, won’t be used as any input name) Figure 71: Import Wizard (1) ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 65...
  • Page 66 To add or update these *.cod code files, please copy them to this path, or install the latest release of the Application Layer GUI. Figure 74: Import files folder ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices...

  • Page 67: Step-By-Step Sample Project Creation

    Depending on the cell, a different wizard will load Edit / delete registers if it's needed Compile and link the project Generate HTML and C code data Download the ROMs ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 67...

  • Page 68: Appendix A - Detailed Register Descriptions

    APPENDIX A – DETAILED REGISTER DESCRIPTIONS This section consists of a detailed description of the ADAV4601 registers. It is broken into 2 sections Default Audio Flow Registers and Main Control Registers. If a user has created their own custom audio flow the Application Layer Software will generate a HTML register map.

  • Page 69: Address 0X0101 Mux Select 2 Register (Default: 0X0000)

    AUXOUT1 output Source for the AUXOUT1 output. 0000 0x0 = reserved 0x1 = ADC1 0x2 = reserved 0x3 = SDIN0 0x4 = SDIN1 0x5 = SDIN2/SRC2 Channel B ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 69...

  • Page 70: Address 0X0102 Main And Headphone 1/Auxout4 Input Trim Register (Default: 0X0E0E)

    0x01 = +13 dB … 0x07 = +7 dB … 0x0E = 0 dB … 0x15 = −7 dB … 0x1B = −13 dB 0x1C = −14 dB ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 70...

  • Page 71: Address 0X0103 Sdo0/Auxout3 And Spdif Input Trim Register (Default: 0X0E0E)

    0x01 = +13 dB … 0x07 = +7 dB … 0x0E = 0 dB … 0x15 = −7 dB 0x1B = −13 dB 0x1C = −14 dB ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 71...

  • Page 72: Address 0X0105 Main Delay Register (Default: 0X0000)

    0x7 = 4 sec 0x8 = 5 sec 0x9 = 6 sec 0xA = 7 sec 0xB = 8 sec 0xC = 9 sec 0xD = 10 sec ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 72...

  • Page 73: Address 0X0107 Main Sever Band Eq Control Register (Default: 0X0018)

    0.5 dB steps. 0x00 = +12 dB 0x01 = +11.5 dB … 0x0A = +7 dB … 0x18 = 0 dB … ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 73...

  • Page 74: Address 0X0108 Main Channel Loudness Register (Default: 0X0000)

    This means that only the frequencies above this frequency are sent to the tweeter output. 0x00 = 50 Hz 0x01 = 60 Hz 0x02 = 70 Hz ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 74...

  • Page 75: Address 0X010A Crossover Trim Register (Default: 0X0E0E)

    0x01 = +13 dB … 0x07 = +7 dB … 0x0E = 0 dB … 0x15 = −7 dB … 0x1B = −13 dB 0x1C = −14 dB ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 75...

  • Page 76: Address 0X010B Adi Bass Control Register (Default: 0X0062)

    Tweeter left balance control 0x010C Bits[11:0] = tweeter left balance control 000010000000 register[27:0] register[27:16] Bits [15:0] Tweeter left balance control 0x010D Bits[15:0] = tweeter left balance control 0000000000000000 register[27:0] register[15:0] ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 76...

  • Page 77: Address 0X010E And Address 0X010F Tweeter Right Balance Control Registers (Default: 0X0080, 0X0000)

    0x0112 Bits[11:0] = woofer right balance control 000010000000 register[27:0] register[27:16] Bits [15:0] Woofer right balance control 0x0113 Bits [15:0] = woofer right balance control 0000000000000000 register[27:0] register[15:0] ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 77...

  • Page 78: Address 0X0114 And Address 0X0115 Main Volume Control Registers (Default: 0X0080, 0X0000)

    0x1 = 10 ms 0x2 = 20 ms 0x3 = 30 ms 0x4 = 40 ms 0x5 = 50 ms 0x6 = 60 ms 0x7 = 70 ms ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 78...

  • Page 79: Address 0X0117 Woofer Peak Limiter Control Register (Default: 0X0F00)

    These register bits control the post gain in the range of +15 dB to −15 dB in +1 01111 dB steps. 0x00 = +15 dB 0x01 = +14 dB … 0x08 = +7 dB … ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 79...
  • Page 80 0x17 = 240 dB/s (~36 ms) 0x18 = 250 dB/s (~34 ms) 0x19 = 260 dB/s (~33 ms) 0x1A = 270 dB/s (~32 ms) 0x1B = 280 dB/s (~31 ms) ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 80...

  • Page 81: Address 0X0118 Headphone 1/Auxout4 Seven Band Eq Control Register (Default: 0X0018)

    Always write as 0 if writing to this register. 0000 Bits[11:0] Woofer left 0x011A Bits[11:0] = Headphone 1/AUXOUT 4 left balance 000010000000 balance control register[27:16] control register[27:0] ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 81...

  • Page 82: Address 0X011C And Address 0X011D Headphone 1/Auxout4 Right Balance Control Registers (Default: 0X0080, 0X0000)

    11b = 70 Hz Bits[4:0] Loudness level These register bits are used to control the required level of loudness. It 00000 can be changed in 1 dB steps. ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 82...

  • Page 83: Address 0X0121 Mute Control Register (Default: 0X0000)

    When set to 1, it enables the lip synchronization delay. 0b = disabled 1b = enabled Bit[12] Enable main EQ When set to 1, it enables the seven band equalizer. 0b = disabled ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 83...
  • Page 84 0b = beeper and channel 1b = beeper only Bit[0] Enable spatializer When set to 1, it enables the ADI spatializer. 0b = disabled 1b = enabled ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 84...

  • Page 85: Address 0X0123 Main Beeper Control Register (Default: 0X0005)

    0x0 = Off 0x1 = 60 Hz 0x2 = 80 Hz 0x3 = 100 Hz 0x4 = 120 Hz 0xE = 320 Hz 0xF = 340 Hz ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 85...

  • Page 86: Address 0X0126 Src Delay Register (Default: 0X0000)

    1b = disabled Bit[0] SRC2 Channel C DSP mute If an error is detected, it mutes the output of SRC2. circuit bypass 0b = enabled 1b = disabled ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 86...

  • Page 87: Main Control Registers

    Used to enable SRC1 Channel A. 0b = disabled 1b = enabled Bit[2] GSB enable When set to 1, the ADAV4601 enters standby mode. 0b = disable standby or not in standby 1b = enable standby or not in standby Bit[1] Audio processor Set to 1 to enable the audio processor.

  • Page 88: Address 0X0004 Serial Port Control 1 Register (Default: 0X0000)

    Used to specify the word width of the data for the synchronous digital width inputs. 00b = 24 bits 01b = 20 bits 10b = 16 bits 11b = not applicable ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 88...

  • Page 89: Address 0X0005 Analog Power Management 1 Register (Default: 0X8000)

    Always write as 0 if writing to this register. Bit[4] Reserved Always write as 0 if writing to this register. Bit[3] HP1DAC right Powers on the HP1 DAC right channel. ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 89...

  • Page 90: Address 0X0007 Digital Power Management Register (Default: 0X0000)

    Always write as 0 if writing to this register. 00000000 Bits[14:12] SPDIF output Selects the source for the SPDIF output. select 000b = output internally generated SPDIF 001b = output SPDIF_IN2 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 90...

  • Page 91: Address 0X000A Misc Control Register (Default: 0X8000)

    Adds dc offset to the DAC Σ-∆ modulator to eliminate idle tones. It is recommended that this bit is disabled before the ADC/DAC engine is powered up Control Register 0x0007[1]. 0b = enabled 1b = disabled ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 91...
  • Page 92 011b = SRC clock/2 (24.576 MHz/512 × FS) 1xxb = modulator clock (6.144 MHz/128 × FS) Bit[0] PLL enable Enables the PLL. 0b = PLL bypassed 1b = PLL enabled ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 92...

  • Page 93: Address 0X000B Headphone Control Register (Default: 0X0000)

    Digout Enable 2 Used to change the function of SPDIF output to serial digital output SDO1. 0b = SPDIF output normal operation 1b = SPDIF output used as SDO1 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 93...

  • Page 94: Address 0X000D Reserved (Default: 0X0721)

    0b = mute pin rising edge clears mute bit 1b = mute clear gated by clear mute bit ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices...

  • Page 95: Address 0X0019 Pwm Status Register (Default: 0X0000)

    1b = mute Bit[2] Clear mute Set to 1 to unmute the ADAV4601 when the external pin has been used to mute the part and the mute clear select bit is set. Having performed the required action, this bit automatically resets to 0.

  • Page 96: Address 0X0080 Reserved (Default: 0X00Fe)

    HP1 Standby Set to 0 after reset, which means the HP amplifier is in normal mode but is still powered down. 0b = Amplifer in normal mode ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 96...

  • Page 97: Address 0X008D Reserved (Default: 0X0220)

    0x1 = 20 bits If 20-bit maximum: 0x5 = 20 bits 0x4 = 19 bits 0x2 = 18 bits 0x6 = 17 bits 0x1 = 16 bits ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 97...

  • Page 98: Address 0X008F Reserved (Default: 0X000A)

    0x50 = sets external EEPROM address 1010000 Address 0x0317 EEPROM Data Address Register (Default: 0x0000) Table 56. Bit No. Bit Name Description Default Bits[15:0] EEPROM start address 0x0000 = default address 0000000000000000 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 98...

  • Page 99: Appendix B - Layout Recommendations

    Figure 75: Ceramic Decoupling Capacitors The ceramic capacitors should be placed as close to the ADAV4601 as possible, governed by the priority listing above. The larger electrolyte capacitors should then placed as closed to the ADAV4601 as possible in the same priority as listed above.

  • Page 100: Pwm Outputs

    GROUND PLANE A split ground plane should be used in the layout of the ADAV4601 with the Analog and Digital Grounds connected underneath the ADAV4601 using a single link. This is to avoid possible ground loop currents in the Analog and Digital ground planes.

  • Page 101: Appendix C - Adav4601 Bill Of Materials

    APPENDIX C – ADAV4601 BILL OF MATERIALS The table below is the bill of materials for the ADAV4601 evaluation board. The minimum BOM required can be found by just using the parts highlighted in green. These correspond to the components shown in Figure 76: Typical Application Diagram.
  • Page 102 C205 220uF CAPACITOR, CASE E 220UF 6.3V FEC 9694340 C145 47uF CAPACITOR, CASE C 47UF 6.3V FEC 9694323 C147 47uF CAPACITOR, CASE C 47UF 6.3V FEC 9694323 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 102...
  • Page 103 FEC 9330402 RESISTOR, 0603 10K FEC 9330399 R111 RESISTOR, 0603 10K FEC 9330399 RESISTOR, 0603 10K FEC 9330399 RESISTOR, 0603 10K FEC 9330399 RESISTOR, 0603 1K FEC 9330380 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 103...
  • Page 104 FEC 9331662 RESISTOR, 0603 0R0 FEC 9331662 RESISTOR, 0603 0R0 FEC 9331662 R126 RESISTOR, 0603 0R0 FEC 9331662 RESISTOR, 0603 10K FEC 9330399 RESISTOR, 0603 10K FEC 9330399 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 104...
  • Page 105 OPTICAL TRANSMITTER 3.3V FEC 1225776 SOCKET, USB MINI-AB SMT + CABLE FEC 9786490 + FEC 1308879 24.576MHz CRYSTAL 24.576 MHZ HC49/US Digikey 300-8512-ND 24MHz CRYSTAL 24MHZ FEC 9509640 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 105...
  • Page 106 PWM4A BCLK1 PWM4B PWM4B LRCLK1 PWM_READY PWM_READY BCLK2 LRCLK2 SPDIF_OUT SPDIF_OUT SDIN0 MCLK_OUT MCLK_OUT SDIN1 SDIN2 SDIN3 SDO0 100nF AVDD (PIN 53) Figure 76: Typical Application Diagram ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 106...

  • Page 107: Appendix D - Schematics

    APPENDIX D – SCHEMATICS ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 107...
  • Page 108 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 108...
  • Page 109 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 109...
  • Page 110 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 110...
  • Page 111 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 111...
  • Page 112 ADAV4601 System Design Document Confidential Information Rev.1 August 2009 Analog Devices Page 112...

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