Impedance Matching Network Examples - Analog Devices ADRV9001 User Manual

Reference Manual
RF PORT INTERFACE INFORMATION
Careful planning is required to select a transmitter balun with a set of external DC bias chokes. It is necessary to find the optimum compromise
between the physical choke size, choke DC resistance (R
chokes, resistance decreases as size increases. However, as choke inductance increases, resistance increases. Therefore, it is undesirable
to use physically small chokes with high inductance as they exhibit the greatest resistance. For example, the voltage drop of a 500 nH, 0603
choke at 100 mA is around 50 mV.
Table 106. Sample Wire-Wound DC Bias Choke Resistance vs. Size vs. Inductance
Inductance (nH)
100
200
300
400
500
600
When selecting a DC bias choke inductor, the shunting impedance of the choke inductor must be high for the transmitter frequency band
to minimize its loading to outputs. Therefore, the self resonant frequency of the selected choke inductor must be higher than the intended
transmitter frequency.
Additionally, the ADRV9001 provides a built-in Transmitter power ramp-up pattern generator to bring transmit power level in a predetermined
way to protect internal devices from sudden voltage spikes, which can happen due to the in-rush current passing through an external DC bias
choke inductor. Also tie the supply side of choke inductors to a capacitor with its self-resonant frequency higher than the transmitter frequency.
When both the transmitter channels are active, tie each transmitter output to its own supply plane through a bias chock inductor or ferrite bead
to reduce coupling between the two transmitters through the same supply feed line.

IMPEDANCE MATCHING NETWORK EXAMPLES

Impedance matching networks are required to achieve the performance levels noted on the data sheet. This section provides example
topologies and components used on the evaluation board. The impedance matching networks provided in this section have not been evaluated
in terms of mean time to failure (MTTF) in high volume production. Contact the component vendors for long-term reliability concerns. Contact
the balun vendors to determine appropriate conditions for DC biasing.
The schematics in Figure 234
the evaluation board schematic to accommodate different component configurations for different frequency ranges. Only one set of standard
microcircuit drawing (SMD) component pads is placed on the board to provide a physical location that can be used for the selected parallel
circuit element. For example, R216, L216, and C216 components only have one set of SMD pads for one SMD component. The schematic
shows that in a generic port impedance matching network, the series elements can be either a resistor, inductor or a capacitor, whereas the
shunt elements can be either an inductor or a capacitor. Only one component of each parallel combination is placed in a practical application.
Note: In some matching circuits, some shunt elements may not be required. All components for a given physical location remain DNI in those
particular applications.
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Figure 233. ADRV9001 RF Transmitter Interface Configuration D
DCR
Resistance (Size: 0603)
0.10
0.15
0.16
0.28
0.45
0.52
and Figure 235 show two or three circuit elements in parallel marked do not include(DNI). This is done on
), and the balun low-frequency insertion loss. In commercially available DC bias
ADRV9001
Resistance (Size: 1206)
0.08
0.10
0.12
0.14
0.15
0.20
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