Power-Supply Recommendations; Power Management Considerations - Analog Devices ADRV9001 User Manual

Reference Manual

POWER-SUPPLY RECOMMENDATIONS

This section provides an overview of the ADRV9001 power-supply solution. The power supply solution for the ADRV9001 changes based on
the desired mode of operation (FDD, TDD, DPD, transmitter tracking, number of active receiver inputs, number of active Tx outputs, internal
LOs vs. external LOs, and 1.0 V power domain). Therefore, it is important to understand the available configurations and optimize the PCB
layout based on the selected mode. This section uses power-supply solutions implemented on the EVB as a reference.

POWER MANAGEMENT CONSIDERATIONS

The ADRV9001 family of devices requires the following four or five different power-supply domains.
1. 1.0 V digital: Connect this supply to the device through the two VDIG_1P0 pins. This is the supply that feeds all digital blocks. Take care
to properly isolate this supply from all analog signals on the PCB to avoid noise corruption. This supply input can have a tolerance of ±5%,
but note that the total tolerance must include the tolerance of the supply device added to the voltage drop of the PCB. In some modes of
operation, this supply can draw high current. It is critical that the input traces for these two inputs be balanced (same impedance for inputs)
and as thick as possible to minimize the I × R drop.
2. 1.0 V analog: These supplies are collectively referred to in the user guide as the VDDA_1P0 supply. This power domain is optional and is
suggested for use only to achieve minimum power consumption. It requires a low noise 1.0 V power domain available in the end system. In
modes of operation where VDDA_1P0 is not used, this 1.0 V power domain is created internally inside the ADRV9001 using internal LDOs.
This power domain supplies voltage to noise sensitive blocks of the ADRV9001. To provide external 1.0 V, ensure very low noise level on
this power domain. This supply input has a tolerance of ±2.5%.
3. 1.3 V analog: These supplies connect to all functional blocks in the device through a number of different input pins. They are collectively
referred to in the user guide as the VDDA_1P3 supply. Each input is treated as a noise-susceptible input, which means proper decoupling
and isolation techniques are followed to avoid crosstalk between channels. The tolerance on these supply inputs is ±2.5%. If VDDA_1P0
is used, some of VDDA_1P3 supply pins change their intended voltage input level from 1.3 V to 1.0 V. This chapter provides a detailed
overview of these modifications.
4. 1.8 V analog: These supplies primarily supply the transmitter outputs. They also supply current for multiple transmitter, receiver, converter,
and auxiliary converter blocks. They are collectively referred to in the user guide as the VDDA_1P8 supply. This supply has a tolerance of
±5%.
5. 1.8 V digital: This is an interface supply. The VDIGIO_1P8 supply is a separate power domain shared with the baseband processor (BBP)
interface. The nominal input voltage on this supply is 1.8 V, with a tolerance of ±5%. This input serves as the voltage reference for the
digital interface (SPI and SSI), DGPIO, and digital control inputs.
IMPORTANT
During operation, supply currents can vary significantly, especially if operating in the TDD mode. The supply must have adequate
capacity to provide the necessary current (as indicated in the user guide) to maintain the performance criteria over all the process
and temperature variations. Analog Devices recommends adding at least 15% margin to all supply maximums to ensure proper
operation under all conditions.
Power-Supply Sequence
The ADRV9001 requires a specific power-up sequence to avoid undesired power-up currents. The optimal power-on sequence requires
VDD_1P0 to power up first. The VDDA_1P3, VDDA_1P8, and VDD_1P8 supplies must then power up after the VDD_1P0 supply. If using
VDDA_1P0, power it up after enabling VDDA_1P3 and VDDA_1P8. Toggle the RESET signal after the power is stabilized before configuration.
The power-down sequence recommendation is similar to power-up. Disable all supplies in any order (or all together) before disabling
VDD_1P0. If such a sequence is not possible, then disable all the sources of the supplies simultaneously to ensure there are no back-feeding
circuits to power down.
Power-Supply Domain Connections
Careful low-noise power management design is a key aspect to ensure good performance.
expected voltage on that pin, and a brief description of routing technique together with the block it powers on the chip. Power supply to the
ADRV9001 is delivered after the star configuration, where a separate trace from a common power plane is used to power each power-supply
pin. Refer to the Printed Circuit Board Layout Recommendations
analog.com
Table 119
section and an evaluation board CAD layout file for details.
ADRV9001
lists the pin number, pin type and name,
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