Interrupts; Register Description; Control Register (Spicr); Table 57. Spi Interrupt Control And Wake-Up Capability - STMicroelectronics ST72361 Auto Series Manual

Serial peripheral interface (SPI)
14.7

Interrupts

Table 57.
Interrupt event
SPI End of Transfer Event
Master Mode Fault Event
Overrun Error
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
14.8

Register description

14.8.1

Control register (SPICR)

Read/ write
Reset value: 0000 xxxx (0xh)
7
SPIE
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault
or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in master mode,
SS = 0 (see
peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0]
bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
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SPI interrupt control and wake-up capability
SPE SPR2
Master mode fault (MODF)). The SPE bit is cleared by reset, so the SPI
Table
Doc ID 12468 Rev 3
Enable
Event
control
flag
bit
SPIF
MODF SPIE
OVR
MSTR CPOL
58.
ST72361xx-Auto
Exit Exit
from from
wait halt
Yes
CPHA SPR1
Yes
No
0
SPR0