Figure 116. Spi Slave Timing Diagram With Cpha = 0; Figure 117. Spi Slave Timing Diagram With Cpha = 1 - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto

Figure 116. SPI slave timing diagram with CPHA = 0

MISO
MOSI
1. Measurement points are done at CMOS levels: 0.3 x V
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.

Figure 117. SPI slave timing diagram with CPHA = 1

MISO
MOSI
1. Measurement points are done at CMOS levels: 0.3 x V
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
SS
INPUT
t
su(SS)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
t
a(SO)
OUTPUT
See note 2
t
su(SI)
INPUT
SS
INPUT
t
su(SS)
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
t
w(SCKH)
t
a(SO)
t
w(SCKL)
See
OUTPUT
Hz
note 2
t
su(SI)
INPUT
Doc ID 12468 Rev 3
t
c(SCK)
t
w(SCKH)
t t
w(SCKL) v(SO)
MSB OUT
BIT6 OUT
t
h(SI)
MSB IN
and 0.7 x V
DD
t
c(SCK)
t
v(SO)
MSB OUT BIT6 OUT
t
h(SI)
MSB IN
and 0.7 x V
DD
Electrical characteristics
t
h(SS)
t
h(SO) t
r(SCK)
t
f(SCK)
LSB OUT
LSB IN
BIT1 IN
DD
t
h(SS)
t
h(SO)
t
r(SCK)
t
f(SCK)
LSB OUT
LSB IN
BIT1 IN
.
DD
t
dis(SO)
See
note 2
t
dis(SO)
See
note 2
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