Output Compare And Time Base Interrupt; External Clock And Event Detector Mode; Input Capture Function; Figure 42. Pwm Signal From 0% To 100% Duty Cycle - STMicroelectronics ST72361 Auto Series Manual

PWM auto-reload timer (ART)

Figure 42. PWM signal from 0% to 100% duty cycle

11.2.6

Output compare and Time base interrupt

On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is
generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF
flag must be reset by the user software. This interrupt can be used as a time base in the
application.
11.2.7

External clock and event detector mode

Using the f
external clock event detector. In this mode, the ARTARR register is used to select the
n number of events to be counted before setting the OVF flag.
EVENT
n = 256 - ARTARR
EVENT
Caution: The external clock function is not available in HALT mode. If HALT mode is used in the
application, prior to executing the HALT instruction, the counter must be disabled by clearing
the TCE bit in the ARTCSR register to avoid spurious counter increments.

Figure 43. External event detector example (3 counts)

11.2.8

Input capture function

Input Capture mode allows the measurement of external signal pulse widths through
ARTICRx registers.
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f
COUNTER
COUNTER
FDh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
external prescaler input clock, the auto-reload timer can be used as an
EXT
f = f
EXT COUNTER
COUNTER
FDh FEh
OVF
Doc ID 12468 Rev 3
ARTARR
= FDh
FEh FFh FDh
ARTARR
= FDh
FFh FDh FEh
ARTCSR READ
INTERRUPT
IF OIE = 1
ST72361xx-Auto
FEh FFh FDh
FFh FDh
ARTCSR READ
INTERRUPT
IF OIE = 1
FEh
t
t