Baud Rate Register (Scibrr); Table 63. Pr Prescaler; Table 64. Transmitter Rate Divider - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
Contains the received or transmitted data character, depending on whether it is read from or
written to.
7
DR7
The data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see
The RDR register provides the parallel interface between the input shift register and the
internal bus (see
15.8.5

Baud rate register (SCIBRR)

Read/ write
Reset value: 0000 0000 (00h)
7
SCP1
Note: When LIN slave mode is disabled, the SCIBRR register controls the conventional baud rate
generator.
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges
Table 63.
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to
the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
Table 64.
LINSCI serial communication interface (LIN master/slave)
DR6 DR5
Figure 77).
Figure 77).
SCP0 SCT2
PR prescaler
PR prescaling factor
1
3
4
13
Transmitter rate divider
TR dividing factor
1
2
4
8
Doc ID 12468 Rev 3
DR4 DR3
SCT1 SCT0
SCP1
SCT2
0
DR2 DR1
SCR2 SCR1
SCP0
0
0
1
0
1
1
SCT1 SCT0
0
1
0
DR0
0
SCR0
0
1
0
1
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