Control Register 3 (Scicr3); Table 75. Lin Sync Break Duration - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is set and cleared by software.
0: no break character is transmitted
1: break characters are transmitted
Note: If the SBK bit is set to "1" and then to "0", the transmitter sends a BREAK word at the end of
the current word.
16.8.4

Control Register 3 (SCICR3)

Read/ write
Reset value: 0000 0000 (00h)
7
-
Bit 7 = Reserved, must be kept cleared.
Bit 6 = LINE LIN Mode Enable.
This bit is set and cleared by software.
0: LIN mode disabled
1: LIN master mode enabled
The LIN Master mode enables the capability to send LIN Synch Breaks (13 low bits) using
the SBK bit in the SCICR2 register.
In transmission, the LIN synch break low phase duration is shown as below:
Table 75.
LINE
Bits 5:4 = Reserved, forced by hardware to 0.
These bits are not used.
Bit 3 = CLKEN Clock Enable.
This bit allows the user to enable the SCLK pin.
0: SLK pin disabled
1: SLK pin enabled
Bit 2 = CPOL Clock Polarity.
This bit allows the user to select the polarity of the clock output on the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock/data relationship (see
and Figure
0: steady low value on SCLK pin outside transmission window.
1: steady high value on SCLK pin outside transmission window.
LINE -
LIN sync break duration
M
0
0
1
0
1
1
93).
LINSCI serial communication interface (LIN master only)
- CLKEN
Number of low bits sent during a LIN synch break
Doc ID 12468 Rev 3
CPOL CPHA
10
11
13
14
Figure 92
0
LBCL
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