Table 46. Pwm Auto-Reload Timer Register Map And Reset Values - STMicroelectronics ST72361 Auto Series Manual

PWM auto-reload timer (ART)
7
0
Bit 7:6 = Reserved, always read as 0.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They determine the trigger event polarity on the
corresponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They enable or disable the Input capture
channel interrupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by software reading the corresponding
ARTICRx register. Each CFx bit indicates that an input capture x has occurred.
0: No input capture on channel x.
1: An input capture has occurred on channel x.
Input Capture Registers (ARTICRx)
Read only
Reset value: 0000 0000 (00h)
7
IC7
Bit 7:0 = IC[7:0] Input Capture Data
These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-
bit auto-reload counter value transferred by the input capture channel x event.
Table 46.
Address
(Hex.)
0031h
0032h
0033h
0034h
100/279
0 CS2
IC6 IC5
PWM auto-reload timer register map and reset values
Register label
PWMDCR3
Reset value
PWMDCR2
Reset value
PWMDCR1
Reset value
PWMDCR0
Reset value
Doc ID 12468 Rev 3
CS1 CIE2
IC4 IC3
7 6 5
DC7 DC6 DC5
0 0 0
DC7 DC6 DC5
0 0 0
DC7 DC6 DC5
0 0 0
DC7 DC6 DC5
0 0 0
ST72361xx-Auto
CIE1 CF2
IC2 IC1
4 3 2
DC4 DC3 DC2
0 0 0
DC4 DC3 DC2
0 0 0
DC4 DC3 DC2
0 0 0
DC4 DC3 DC2
0 0 0
0
CF1
0
IC0
1 0
DC1 DC0
0 0
DC1 DC0
0 0
DC1 DC0
0 0
DC1 DC0
0 0