Functional Description; Counter - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
12.3

Functional description

12.3.1

Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter Register (CR):
●
Counter High Register (CHR) is the most significant byte (MS Byte).
●
Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
●
Alternate Counter High Register (ACHR) is the m
● Alternate Counter Low Register (ACLR) is the least significant byte (LS
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the
Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM
mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 50. The value in the counter register repeats every 131072, 262144 or 524288 CPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be f /2, f /4, f /8 or an external frequency.
CPU CPU CPU
Doc ID 12468 Rev 3
byte
ost significant (MS Byte).
16-bit timer
).
Byte
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