Changing The Conversion Channel; Adcdr Consistency; Low Power Modes; Interrupts - STMicroelectronics ST72361 Auto Series Manual

10-bit A/D converter (ADC)
17.3.3

Changing the conversion channel

The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
17.3.4

ADCDR consistency

If an End Of Conversion event occurs after software has read the ADCDRLSB but before it
has read the ADCDRMSB, there would be a risk that the two values read would belong to
different samples.
To guarantee consistency:
● The ADCDRL and the ADCDRH registers are locked when the ADCCRL is read
●
The ADCDRL and the ADCDRH registers are unlocked when the ADCDRH register is
read or when ADON is reset.
This is important, as the ADCDR register will not be updated until the ADCDRH register is
read.
17.4

Low power modes

Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 82.
Mode
WAIT
HALT
17.5

Interrupts

None.
17.6

Register description

17.6.1

Control/status register (ADCCSR)

Read/ write (except bit 7 read only)
Reset value: 0000 0000 (00h)
7
EOC
216/279
Effect of low power modes on ADC
No effect on A/D converter
A/D converter disabled.
After wakeup from Halt mode, the A/D converter requires a stabilization time
t (see Electrical Characteristics) before accurate conversions can be
STAB
performed.
SPEED ADON
Doc ID 12468 Rev 3
Description
SLOW CH3
ST72361xx-Auto
CH2 CH1
0
CH0