STMicroelectronics ST72361 Auto Series Manual page 130

8-bit timer (TIM8)
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OC
Timing resolution is one count of the free running counter: (f
Procedure
To use the output compare function, select the following in the CR2 register:
●
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
●
Select the timer clock (CC[1:0]) (see
And select the following in the CR1 register:
●
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
●
Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:
●
OCFi bit is set.
● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
●
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OC R register value required for a specific timing application can be calculated using
i
the following formula:
Where:

t =
f =
CPU
=
PRESC
Table 55)
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set.
2. An access (read or write) to the OCiR register.
Note: 1 Once the OCIE bit is set both output compare features may trigger interrupt requests. If only
one is needed in the application, the interrupt routine software needs to discard the
unwanted compare interrupt. This can be done by checking the OCF1 and OCF2 flags and
resetting them both.
2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
3 When the timer clock is f
OCiR register value (see
130/279
R value to 00h.
i
Output compare period (in seconds)
PLL output x2 clock frequency in hertz (or f
Timer prescaler factor (2, 4, 8 or 8000 depending on CC[1:0] bits, see
/2, OCFi and OCMPi are set while the counter value equals the
CPU
Figure 66). This behavior is the same in OPM or PWM mode.
Doc ID 12468 Rev 3
Table 55).
t
 f
*
CPU
OCiR =
PRESC
OSC
ST72361xx-Auto
).
CPU / CC[1:0]
/2 if PLL is not enabled)