Low Power Modes; Interrupts; Table 61. Effect Of Low Power Modes On Sci; Table 62. Sci Interrupt Control And Wake-Up Capability - STMicroelectronics ST72361 Auto Series Manual

LINSCI serial communication interface (LIN master/slave)
Example 2: data = 00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS
bit = 0).
Odd parity
The parity bit is calculated to obtain an odd number of "1s" inside the character made of the
7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example 3: data = 00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit
= 1).
Transmission mode
If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted
but is changed by the parity bit.
Reception mode
If the PCE bit is set then the interface checks if the received data byte has an even number
of "1s" if even parity is selected (PS = 0) or an odd number of "1s" if odd parity is selected
(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is
generated if PCIE is set in the SCICR1 register.
15.6

Low power modes

Table 61.
Mode
WAIT
HALT
15.7

Interrupts

Table 62.
Transmit Data Register Empty
Transmission Complete
Received Data Ready to be Read
Overrun Error or LIN Synch Error
Detected
Idle Line Detected
Parity Error
LIN Header Detection
166/279
Effect of low power modes on SCI
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
SCI interrupt control and wake-up capability
Interrupt event
Doc ID 12468 Rev 3
Description
Enable
Event
control
flag
bit
TDRE TIE
TC TCIE
RDRF
RIE
OR/LHE
IDLE ILIE
PE PIE
LHDF LHIE
ST72361xx-Auto
Exit Exit
from from
Wait Halt
Yes No