Internal Watchdog Reset; System Integrity Management (Si); Low Voltage Detector (Lvd); Figure 14. Reset Sequences - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
The device RESET pin acts as an output that is pulled low when V
V < V
DD IT-
The LVD filters spikes on V
5.5.5

Internal watchdog reset

The RESET sequence generated by a internal Watchdog counter overflow is shown in
Figure 14.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t

Figure 14. Reset sequences

5.6

System integrity management (SI)

The System Integrity Management block contains the Low Voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
5.6.1

Low voltage detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the V
voltage is below a V
as the power-down keeping the ST7 in reset.
The V
IT-(LVD)
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD reset circuitry generates a reset when V
●
V
IT+(LVD)
●
V
IT-(LVD)
(falling edge) as shown in
larger than t
DD
w(RSTL)out
V
DD
V
IT+(LVD)
V
IT-(LVD)
LVD
RESET
RUN
ACTIVE PHASE
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
reference value. This means that it secures the power-up as well
IT-(LVD)
reference value for a voltage drop is lower than the V
when V is rising
DD
when V is falling
DD
Doc ID 12468 Rev 3
Supply, reset and clock management
Figure 14.
to avoid parasitic resets.
g(VDD)
.
EXTERNAL
RESET
RUN
ACTIVE
PHASE
t
h(RSTL)in
WATCHDOG UNDERFLOW
is below:
DD
< V (rising edge) or
DD IT+
WATCHDOG
RESET
RUN RUN
ACTIVE
PHASE
t
w(RSTL)out
INTERNAL RESET (256 or 4096 T )
CPU
VECTOR FETCH
supply
DD
reference value
IT+(LVD)
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