Error Flags; Master Mode Fault (Modf); Figure 74. Data Clock Timing Diagram - STMicroelectronics ST72361 Auto Series Manual

Serial peripheral interface (SPI)
MISO pin and the MOSI pin are directly connected between the master and the slave
device.
Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.

Figure 74. Data clock timing diagram

14.5

Error flags

14.5.1

Master mode fault (MODF)

Master mode fault occurs when the master device's SS pin is pulled low.
When a Master mode fault occurs:
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
●
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
●
The MSTR bit is reset, thus forcing the device into slave mode.
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SCK
(CPOL = 1)
SCK
(CPOL = 0)
MSBit Bit 6
MISO
(from master)
MSBit Bit 6
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO MSBit Bit 6
(from master)
MOSI MSBit Bit 6
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
Doc ID 12468 Rev 3
CPHA = 1
Bit 4 Bit3 Bit 2
Bit 5
Bit 4 Bit3 Bit 2
Bit 5
CPHA = 0
Bit 4 Bit3 Bit 2
Bit 5
Bit 4 Bit3 Bit 2
Bit 5
ST72361xx-Auto
Bit 1 LSBit
Bit 1 LSBit
Bit 1 LSBit
Bit 1 LSBit